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| author | Fred Fish <fnf@specifix.com> | 1997-01-19 18:33:10 +0000 |
|---|---|---|
| committer | Fred Fish <fnf@specifix.com> | 1997-01-19 18:33:10 +0000 |
| commit | 8fdffbc4b33c081fad2b32f831812a4955b5a9fe (patch) | |
| tree | dbf30f7c1ae45f6e3ea6cbf4ae12ed79b47fc827 /opcodes/tic80-opc.c | |
| parent | 15cb042bc12338f7889e25fc541879b754457288 (diff) | |
| download | gdb-8fdffbc4b33c081fad2b32f831812a4955b5a9fe.zip gdb-8fdffbc4b33c081fad2b32f831812a4955b5a9fe.tar.gz gdb-8fdffbc4b33c081fad2b32f831812a4955b5a9fe.tar.bz2 | |
* tic80-dis.c (print_insn_tic80): Broke excessively long
function up into several smaller ones and arranged for
the instruction printing function to be callable recursively
to print vector instructions that have both a load and a
math instruction packed into a single opcode.
* tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
to explain why it comes after the other vector opcodes.
Diffstat (limited to 'opcodes/tic80-opc.c')
| -rw-r--r-- | opcodes/tic80-opc.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/opcodes/tic80-opc.c b/opcodes/tic80-opc.c index 6e2e260..bf8dc4f 100644 --- a/opcodes/tic80-opc.c +++ b/opcodes/tic80-opc.c @@ -831,14 +831,17 @@ const struct tic80_opcode tic80_opcodes[] = { {"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, {"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, - /* Vector Load Data Into Register */ + /* Vector Floating-Point Multiply and Add to Accumulator */ + + /* Vector Load Data Into Register - Note that this comes after all the other + vector instructions so that the disassembler will always print the load instruction + second for vector instructions that have two instructions in the same opcode. */ {"vld0.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, {"vld1.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, {"vld0.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, {"vld1.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, - {"xnor", OP_LI(0x333), MASK_LI, 0, FIXME}, {"xnor", OP_REG(0x332), MASK_REG, 0, FIXME}, {"xnor", OP_SI(0x19), MASK_SI, 0, FIXME}, |