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| author | Nick Clifton <nickc@redhat.com> | 2016-02-04 09:55:10 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2016-02-04 09:55:10 +0000 |
| commit | c1d9289fef41b82aa22f63f74aa8e730ec898d3c (patch) | |
| tree | e477a2b77b58e8d51a359f02cba511bc00f85873 /opcodes/spu-opc.c | |
| parent | 1b18aa1e79a0b343087d08075f117e821c33b930 (diff) | |
| download | gdb-c1d9289fef41b82aa22f63f74aa8e730ec898d3c.zip gdb-c1d9289fef41b82aa22f63f74aa8e730ec898d3c.tar.gz gdb-c1d9289fef41b82aa22f63f74aa8e730ec898d3c.tar.bz2 | |
Fix the encoding of the MSP430's RRUX instruction.
PR target/19561
opcdoe * msp430-dis.c (print_insn_msp430): Add a special case for
decoding an RRC instruction with the ZC bit set in the extension
word.
include * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
(RRUX): Synthesise using case 2 rather than 7.
gas * config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2
to handle encoding of RRUX instruction.
* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
shift instructions.
* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
Diffstat (limited to 'opcodes/spu-opc.c')
0 files changed, 0 insertions, 0 deletions