bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.

This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.

Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header.  However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.

bfd/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* archures.c (bfd_mach_sparc_v8plusc): Define.
	(bfd_mach_sparc_v9c): Likewise.
	(bfd_mach_sparc_v8plusd): Likewise.
	(bfd_mach_sparc_v9d): Likewise.
	(bfd_mach_sparc_v8pluse): Likewise.
	(bfd_mach_sparc_v9e): Likewise.
	(bfd_mach_sparc_v8plusv): Likewise
	(bfd_mach_sparc_v9v): Likewise.
	(bfd_mach_sparc_v8plusm): Likewise.
	(bfd_mach_sparc_v9m): Likewise.
	(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
	(bfd_mach_sparc_64bit_p): Likewise.
	* bfd-in2.h: Regenerate.
	* cpu-sparc.c (arch_info_struct): Add entries for
	bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
	* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
	and bfd_mach_sparc_v9{c,d,e,v,m}.
	* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.

include/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/sparc.h (enum sparc_opcode_arch_val): Add
	SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
	SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
	SPARC_OPCODE_ARCH_V9M.

opcodes/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
	(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
	bfd_mach_sparc_v9{c,d,e,v,m}.
	* sparc-opc.c (MASK_V9C): Define.
	(MASK_V9D): Likewise.
	(MASK_V9E): Likewise.
	(MASK_V9V): Likewise.
	(MASK_V9M): Likewise.
	(v6): Add MASK_V9{C,D,E,V,M}.
	(v6notlet): Likewise.
	(v7): Likewise.
	(v8): Likewise.
	(v9): Likewise.
	(v9andleon): Likewise.
	(v9a): Likewise.
	(v9b): Likewise.
	(v9c): Define.
	(v9d): Likewise.
	(v9e): Likewise.
	(v9v): Likewise.
	(v9m): Likewise.
	(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.

1 files changed, 44 insertions, 8 deletions

diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index e40ce37..14e4cce 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -37,17 +37,25 @@
 #define MASK_V9		SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
 #define MASK_V9A	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
 #define MASK_V9B	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
+#define MASK_V9C	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C)
+#define MASK_V9D	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D)
+#define MASK_V9E	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E)
+#define MASK_V9V	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V)
+#define MASK_V9M	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M)
 
 /* Bit masks of architectures supporting the insn.  */
 
 #define v6		(MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
 			 | MASK_SPARCLET | MASK_SPARCLITE \
-			 | MASK_V9 | MASK_V9A | MASK_V9B)
+			 | MASK_V9 | MASK_V9A | MASK_V9B \
+                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
 /* v6 insns not supported on the sparclet.  */
 #define v6notlet	(MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
-			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
+			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
+                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
 #define v7		(MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \
-			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
+			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
+                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
 /* Although not all insns are implemented in hardware, sparclite is defined
    to be a superset of v8.  Unimplemented insns trap and are then theoretically
    implemented in software.
@@ -55,16 +63,28 @@
    suggest it is.  Rather than complicating things, the sparclet assembler
    recognizes all v8 insns.  */
 #define v8		(MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \
-			 | MASK_V9 | MASK_V9A | MASK_V9B)
+			 | MASK_V9 | MASK_V9A | MASK_V9B \
+                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
 #define sparclet	(MASK_SPARCLET)
 /* sparclet insns supported by leon.  */
 #define letandleon	(MASK_SPARCLET | MASK_LEON)
 #define sparclite	(MASK_SPARCLITE)
-#define v9		(MASK_V9 | MASK_V9A | MASK_V9B)
+#define v9		(MASK_V9 | MASK_V9A | MASK_V9B \
+                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
 /* v9 insns supported by leon.  */
-#define v9andleon	(MASK_V9 | MASK_V9A | MASK_V9B | MASK_LEON)
-#define v9a		(MASK_V9A | MASK_V9B)
-#define v9b		(MASK_V9B)
+#define v9andleon	(MASK_V9 | MASK_V9A | MASK_V9B \
+                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
+                         | MASK_LEON)
+#define v9a		(MASK_V9A | MASK_V9B \
+                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
+#define v9b		(MASK_V9B \
+                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
+#define v9c		(MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
+#define v9d		(MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
+#define v9e		(MASK_V9E | MASK_V9V | MASK_V9M)
+#define v9v		(MASK_V9V | MASK_V9M)
+#define v9m		(MASK_V9M)
+
 /* v6 insns not supported by v9.  */
 #define v6notv9		(MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
 			 | MASK_SPARCLET | MASK_SPARCLITE)
@@ -89,6 +109,22 @@ const struct sparc_opcode_arch sparc_opcode_archs[] =
   { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
   /* v9 with cheetah additions */
   { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
+  /* v9 with UA2005 and T1 additions.  */
+  { "v9c", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
+            | MASK_V9C) },
+  /* v9 with UA2007 and T3 additions.  */
+  { "v9d", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
+            | MASK_V9C | MASK_V9D) },
+  /* v9 with OSA2011 and T4 additions modulus integer multiply-add.  */
+  { "v9e", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
+            | MASK_V9C | MASK_V9D | MASK_V9E) },
+  /* V9 with OSA2011 and T4 additions, integer multiply and Fujitsu fp
+     multiply-add.  */
+  { "v9v", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
+            | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V) },
+  /* v9 with OSA2015 and M7 additions.  */
+  { "v9m", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
+            | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) },
   { NULL, 0 }
 };