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| author | Joern Rennecke <joern.rennecke@embecosm.com> | 2004-02-26 16:14:42 +0000 |
|---|---|---|
| committer | Joern Rennecke <joern.rennecke@embecosm.com> | 2004-02-26 16:14:42 +0000 |
| commit | 6a5709a5a18aabe5b4f7f14ddfd758af3eaa9a31 (patch) | |
| tree | 5cba78bb8d599578b49d7852b8b0152b3c172eee /opcodes/sh-dis.c | |
| parent | c89dc5d424056423307e7cd62896c5dc16e8d107 (diff) | |
| download | gdb-6a5709a5a18aabe5b4f7f14ddfd758af3eaa9a31.zip gdb-6a5709a5a18aabe5b4f7f14ddfd758af3eaa9a31.tar.gz gdb-6a5709a5a18aabe5b4f7f14ddfd758af3eaa9a31.tar.bz2 | |
2004-02-23 Andrew Stubbs <andrew.stubbs@superh.com>
gas:
* tc-sh.c (build_Mytes): Add REG_N_D and REG_N_B01
nibble types to assembler.
opcodes:
* sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
ensure that double registers have even numbers.
Add REG_N_B01 for nn01 (binary 01) nibble to ensure
that reserved instruction 0xfffd does not decode the same
as 0xfdfd (ftrv).
* sh-opc.h: Add REG_N_D nibble type and use it whereever
REG_N refers to a double register.
Add REG_N_B01 nibble type and use it instead of REG_NM
in ftrv.
Adjust the bit patterns in a few comments.
Diffstat (limited to 'opcodes/sh-dis.c')
| -rw-r--r-- | opcodes/sh-dis.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c index 70fdffb..2512f96 100644 --- a/opcodes/sh-dis.c +++ b/opcodes/sh-dis.c @@ -577,12 +577,21 @@ print_insn_sh (memaddr, info) case IMM1_8BY4: imm = ((nibs[2] << 4) | nibs[3]) << 2; goto ok; + case REG_N_D: + if ((nibs[n] & 1) != 0) + goto fail; + /* fall through */ case REG_N: rn = nibs[n]; break; case REG_M: rm = nibs[n]; break; + case REG_N_B01: + if ((nibs[n] & 0x3) != 1 /* binary 01 */) + goto fail; + rn = (nibs[n] & 0xc) >> 2; + break; case REG_NM: rn = (nibs[n] & 0xc) >> 2; rm = (nibs[n] & 0x3); |