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| author | Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | 2008-08-15 12:10:21 +0000 |
|---|---|---|
| committer | Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | 2008-08-15 12:10:21 +0000 |
| commit | 7dc6076f0ce4ca5d95e4a564677a3af3a253ea3c (patch) | |
| tree | 43edf8d5f31cfe5a04b04f8a253dae8e8e67269c /opcodes/s390-opc.c | |
| parent | 7357c5b6a63767cbfc54cce1886c5ed262031f19 (diff) | |
| download | gdb-7dc6076f0ce4ca5d95e4a564677a3af3a253ea3c.zip gdb-7dc6076f0ce4ca5d95e4a564677a3af3a253ea3c.tar.gz gdb-7dc6076f0ce4ca5d95e4a564677a3af3a253ea3c.tar.bz2 | |
2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
* s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/esa-g5.d: lxr operands are floating point.
* gas/s390/esa-g5.s: Likewise.
* gas/testsuite/gas/s390/zarch-z9-ec.d: rrdtr, rrxtr third
operands is gpr.
* gas/testsuite/gas/s390/zarch-z9-ec.s: Likewise.
Diffstat (limited to 'opcodes/s390-opc.c')
| -rw-r--r-- | opcodes/s390-opc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index d7a114b..d31ca1e 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -274,6 +274,7 @@ const struct s390_operand s390_operands[] = #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */ +#define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. clrt */ #define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ @@ -378,6 +379,7 @@ const struct s390_operand s390_operands[] = #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } #define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |