diff options
| author | Andreas Krebbel <krebbel@linux.vnet.ibm.com> | 2015-04-27 10:29:16 +0200 |
|---|---|---|
| committer | Andreas Krebbel <krebbel@linux.vnet.ibm.com> | 2015-04-27 10:29:16 +0200 |
| commit | 3b78cfe1033fafa6ca36c69cf8587c1bd96996ca (patch) | |
| tree | 619162201e321695faabb815288edf72aedb6915 /opcodes/s390-opc.c | |
| parent | 963a4320b49a3c55af02b36a492a10ba04a08e8a (diff) | |
| download | gdb-3b78cfe1033fafa6ca36c69cf8587c1bd96996ca.zip gdb-3b78cfe1033fafa6ca36c69cf8587c1bd96996ca.tar.gz gdb-3b78cfe1033fafa6ca36c69cf8587c1bd96996ca.tar.bz2 | |
S/390: Fixes for z13 instructions.
opcodes/
* s390-opc.c: New instruction type VV0UU2.
* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
and WFC.
gas/testsuite/
* gas/s390/zarch-z13.d: Fix tests for VFCE, VLDE, VFSQ, WFK, and
WFC.
* gas/s390/zarch-z13.s: Likewise.
Diffstat (limited to 'opcodes/s390-opc.c')
| -rw-r--r-- | opcodes/s390-opc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index a803579..befd171 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -484,6 +484,7 @@ const struct s390_operand s390_operands[] = #define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */ #define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/ #define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */ +#define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */ #define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */ #define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */ #define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */ @@ -690,6 +691,7 @@ const struct s390_operand s390_operands[] = #define MASK_VRR_VV0U { 0xff, 0x00, 0xff, 0xff, 0x00, 0xff } #define MASK_VRR_VV0U2 { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } #define MASK_VRR_VV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } +#define MASK_VRR_VV0UU2 { 0xff, 0x00, 0xff, 0xf0, 0x00, 0xff } #define MASK_VRR_VV0UU8 { 0xff, 0x00, 0xff, 0x08, 0xf0, 0xff } #define MASK_VRR_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } #define MASK_VRR_VVVUU0V { 0xff, 0x00, 0x00, 0x0f, 0x00, 0xff } |