bfd

        * Makefile.am (ALL_MACHINES): Add cpu-rx.lo.
        (ALL_MACHINES_CFILES): Add cpu-rx.c.
        (BFD32_BACKENDS): Add elf32-rx.lo.
        (BFD32_BACKENDS_CFILES): Add elf32-rx.c.
        * archures.c (bfd_architecture): Add bfd_arch_rx and bfd_mach_rx.
        Export bfd_rx_arch.
        (bfd_archures_list): Add bfd_rx_arch.
        * config.bfd: Add entry for rx-*-elf.
        * configure.in: Add entries for bfd_elf32_rx_le_vec and
        bfd_elf32_rx_be_vec.
        * reloc.c: Add RX relocations.
        * targets.c: Add RX target vectors.
        * Makefile.in: Regenerate.
        * bfd-in2.h: Regenerate.
        * configure: Regenerate.
        * libbfd.h: Regenerate.
        * cpu-rx.c: New file.
        * elf32-rx.c: New file.

binutils
        * readelf.c: Add support for RX target.
        * MAINTAINERS: Add DJ and NickC as maintainers for RX.

gas
        * Makefile.am: Add RX target.
        * configure.in: Likewise.
        * configure.tgt: Likewise.
        * read.c (do_repeat_with_expander): New function.
        * read.h: Provide a prototype for do_repeat_with_expander.
        * doc/Makefile.am: Add RX target documentation.
        * doc/all.texi: Likewise.
        * doc/as.texinfo: Likewise.
        * Makefile.in: Regenerate.
        * NEWS: Mention support for RX architecture.
        * configure: Regenerate.
        * doc/Makefile.in: Regenerate.
        * config/rx-defs.h: New file.
        * config/rx-parse.y: New file.
        * config/tc-rx.h: New file.
        * config/tc-rx.c: New file.
        * doc/c-rx.texi: New file.

gas/testsuite
        * gas/rx: New directory.
        * gas/rx/*: New set of test cases.
        * gas/elf/section2.e-rx: New expected output file.
        * gas/all/gas.exp: Add support for RX target.
        * gas/elf/elf.exp: Likewise.
        * gas/lns/lns.exp: Likewise.
        * gas/macros/macros.exp: Likewise.

include
        * dis-asm.h: Add prototype for print_insn_rx.

include/elf
        * rx.h: New file.

include/opcode
        * rx.h: New file.

ld
        * Makefile.am: Add rules to build RX emulation.
        * configure.tgt: Likewise.
        * NEWS: Mention support for RX architecture.
        * Makefile.in: Regenerate.
        * emulparams/elf32rx.sh: New file.
        * emultempl/rxelf.em: New file.

opcodes
        * Makefile.am: Add RX files.
        * configure.in: Add support for RX target.
        * disassemble.c: Likewise.
        * Makefile.in: Regenerate.
        * configure: Regenerate.
        * opc2c.c: New file.
        * rx-decode.c: New file.
        * rx-decode.opc: New file.
        * rx-dis.c: New file.

1 files changed, 199 insertions, 0 deletions

diff --git a/opcodes/rx-dis.c b/opcodes/rx-dis.c
new file mode 100644
index 0000000..3413b1d
--- /dev/null
+++ b/opcodes/rx-dis.c
@@ -0,0 +1,199 @@
+/* Disassembler code for Renesas RX.
+   Copyright 2008, 2009 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+   Written by DJ Delorie.
+
+   This file is part of the GNU opcodes library.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include <stdio.h>
+
+#include "bfd.h"
+#include "dis-asm.h"
+#include "opcode/rx.h"
+
+typedef struct
+{
+  bfd_vma pc;
+  disassemble_info * dis;
+} RX_Data;
+
+static int
+rx_get_byte (void * vdata)
+{
+  bfd_byte buf[1];
+  RX_Data *rx_data = (RX_Data *) vdata;
+
+  rx_data->dis->read_memory_func (rx_data->pc,
+				  buf,
+				  1,
+				  rx_data->dis);
+
+  rx_data->pc ++;
+  return buf[0];
+}
+
+static char const * size_names[] =
+{
+  "", ".b", ".ub", ".b", ".w", ".uw", ".w", ".a", ".l"
+};
+
+static char const * opsize_names[] =
+{
+  "", ".b", ".b", ".b", ".w", ".w", ".w", ".a", ".l"
+};
+
+static char const * register_names[] =
+{
+  /* general registers */
+  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+  /* control register */
+  "psw", "pc", "usp", "fpsw", "cpen", "", "", "wr",
+  "bpsw", "bpc", "isp", "fintv", "intb", "", "", "",
+  "pbp", "pben", "", "", "", "", "", "",
+  "bbpsw", "bbpc", "", "", "", "", "", ""
+};
+
+static char const * condition_names[] =
+{
+  /* condition codes */
+  "eq", "ne", "c", "nc", "gtu", "leu", "pz", "n",
+  "ge", "lt", "gt", "le", "o", "no", "always", "never"
+};
+
+static const char * flag_names[] =
+{
+  "c", "z", "s", "o", "", "", "", "",
+  "", "", "", "", "", "", "", "",
+  "i", "u", "", "", "", "", "", ""
+  "", "", "", "", "", "", "", "",
+};
+
+int
+print_insn_rx (bfd_vma addr, disassemble_info * dis)
+{
+  int rv;
+  RX_Data rx_data;
+  RX_Opcode_Decoded opcode;
+  const char * s;
+
+  rx_data.pc = addr;
+  rx_data.dis = dis;
+
+  rv = rx_decode_opcode (addr, &opcode, rx_get_byte, &rx_data);
+
+  dis->bytes_per_line = 10;
+
+#define PR (dis->fprintf_func)
+#define PS (dis->stream)
+#define PC(c) PR (PS, "%c", c)
+
+  for (s = opcode.syntax; *s; s++)
+    {
+      if (*s != '%')
+	{
+	  PC (*s);
+	}
+      else
+	{
+	  RX_Opcode_Operand * oper;
+	  int do_size = 0;
+	  int do_hex = 0;
+	  int do_addr = 0;
+
+	  s ++;
+
+	  if (*s == 'S')
+	    {
+	      do_size = 1;
+	      s++;
+	    }
+	  if (*s == 'x')
+	    {
+	      do_hex = 1;
+	      s++;
+	    }
+	  if (*s == 'a')
+	    {
+	      do_addr = 1;
+	      s++;
+	    }
+
+	  switch (*s)
+	    {
+	    case '%':
+	      PC ('%');
+	      break;
+
+	    case 's':
+	      PR (PS, "%s", opsize_names[opcode.size]);
+	      break;
+
+	    case '0':
+	    case '1':
+	    case '2':
+	      oper = opcode.op + *s - '0';
+	      if (do_size)
+		{
+		  if (oper->type == RX_Operand_Indirect)
+		    PR (PS, "%s", size_names[oper->size]);
+		}
+	      else
+		switch (oper->type)
+		  {
+		  case RX_Operand_Immediate:
+		    if (do_addr)
+		      dis->print_address_func (oper->addend, dis);
+		    else if (do_hex
+			     || oper->addend > 999
+			     || oper->addend < -999)
+		      PR (PS, "%#x", oper->addend);
+		    else
+		      PR (PS, "%d", oper->addend);
+		    break;
+		  case RX_Operand_Register:
+		    PR (PS, "%s", register_names[oper->reg]);
+		    break;
+		  case RX_Operand_Indirect:
+		    if (oper->addend)
+		      PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
+		    else
+		      PR (PS, "[%s]", register_names[oper->reg]);
+		    break;
+		  case RX_Operand_Postinc:
+		    PR (PS, "[%s+]", register_names[oper->reg]);
+		    break;
+		  case RX_Operand_Predec:
+		    PR (PS, "[-%s]", register_names[oper->reg]);
+		    break;
+		  case RX_Operand_Condition:
+		    PR (PS, "%s", condition_names[oper->reg]);
+		    break;
+		  case RX_Operand_Flag:
+		    PR (PS, "%s", flag_names[oper->reg]);
+		    break;
+		  default:
+		    PR (PS, "[???]");
+		    break;
+		  }
+	    }
+	}
+    }
+
+  return rv;
+}