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| author | Vinay Kumar <vinay.g@kpit.com> | 2015-10-27 15:24:40 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2015-10-27 15:24:40 +0000 |
| commit | c2f2875869a3e427435ea04bcd416ee2f99e7ee9 (patch) | |
| tree | aa46e5203bb211b028f561355b2ec855628b157f /opcodes/rl78-decode.opc | |
| parent | 709b551853919f47b58aafbb95fd00a98bcaf76c (diff) | |
| download | gdb-c2f2875869a3e427435ea04bcd416ee2f99e7ee9.zip gdb-c2f2875869a3e427435ea04bcd416ee2f99e7ee9.tar.gz gdb-c2f2875869a3e427435ea04bcd416ee2f99e7ee9.tar.bz2 | |
Fix RL78 disassembly of DE+offset addressing to always show the offset, even when zero.
PR binutils/19159
opcodes * rl78-decode.opc (MOV): Added offset to DE register in index
addressing mode.
* rl78-decode.c: Regenerate.
test * gas/rl78/pr19159.s: New test source file.
* gas/rl78/pr19159.d: New test case.
* gas/rl78/rl78.exp: Run the new test.
Diffstat (limited to 'opcodes/rl78-decode.opc')
| -rw-r--r-- | opcodes/rl78-decode.opc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/opcodes/rl78-decode.opc b/opcodes/rl78-decode.opc index 28362c1..6e84959 100644 --- a/opcodes/rl78-decode.opc +++ b/opcodes/rl78-decode.opc @@ -614,10 +614,10 @@ rl78_decode_opcode (unsigned long pc AU, /** 1001 1001 mov %e0, %1 */ ID(mov); DM(DE, 0); SR(A); -/** 1100 1010 mov %e0, #%1 */ +/** 1100 1010 mov %ea0, #%1 */ ID(mov); DM(DE, IMMU(1)); SC(IMMU(1)); -/** 1001 1010 mov %e0, %1 */ +/** 1001 1010 mov %ea0, %1 */ ID(mov); DM(DE, IMMU(1)); SR(A); /** 1001 1011 mov %e0, %1 */ @@ -647,7 +647,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 1000 1001 mov %0, %e1 */ ID(mov); DR(A); SM(DE, 0); -/** 1000 1010 mov %0, %e1 */ +/** 1000 1010 mov %0, %ea1 */ ID(mov); DR(A); SM(DE, IMMU(1)); /** 1000 1011 mov %0, %e1 */ @@ -818,7 +818,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 1011 1001 movw %e0, %1 */ ID(mov); W(); DM(DE, 0); SR(AX); -/** 1011 1010 movw %e0, %1 */ +/** 1011 1010 movw %ea0, %1 */ ID(mov); W(); DM(DE, IMMU(1)); SR(AX); /** 1011 1011 movw %e0, %1 */ @@ -837,7 +837,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 1010 1001 movw %0, %e1 */ ID(mov); W(); DR(AX); SM(DE, 0); -/** 1010 1010 movw %0, %e1 */ +/** 1010 1010 movw %0, %ea1 */ ID(mov); W(); DR(AX); SM(DE, IMMU(1)); /** 1010 1011 movw %0, %e1 */ @@ -1206,7 +1206,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 0110 0001 1010 1110 xch %0, %e1 */ ID(xch); DR(A); SM(DE, 0); -/** 0110 0001 1010 1111 xch %0, %e1 */ +/** 0110 0001 1010 1111 xch %0, %ea1 */ ID(xch); DR(A); SM(DE, IMMU(1)); /** 0110 0001 1010 1100 xch %0, %e1 */ |