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| author | Vinay Kumar <vinay.g@kpit.com> | 2015-10-27 14:00:40 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2015-10-27 14:00:40 +0000 |
| commit | 02f12cd4669463a1b2346145808213adeb303e2d (patch) | |
| tree | 173fc4a7a578830e6145027aeb31191d7229febb /opcodes/rl78-decode.opc | |
| parent | c6486df5f1400d90a13df5c6dbd96aeaccf8225b (diff) | |
| download | gdb-02f12cd4669463a1b2346145808213adeb303e2d.zip gdb-02f12cd4669463a1b2346145808213adeb303e2d.tar.gz gdb-02f12cd4669463a1b2346145808213adeb303e2d.tar.bz2 | |
Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, even when zero.
PR binutils/19157
opcodes * rl78-decode.opc: Add 'a' print operator to mov instructions
using stack pointer plus index addressing.
* rl78-decode.c: Regenerate.
tests * gas/rl78: New directory.
* gas/rl78/rl78.exp: New test driver.
* gas/rl78/pr19157.s: New test source file.
* gas/rl78/pr19157.d: New test case.
Diffstat (limited to 'opcodes/rl78-decode.opc')
| -rw-r--r-- | opcodes/rl78-decode.opc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/opcodes/rl78-decode.opc b/opcodes/rl78-decode.opc index 6475b62..8bb8d09 100644 --- a/opcodes/rl78-decode.opc +++ b/opcodes/rl78-decode.opc @@ -635,10 +635,10 @@ rl78_decode_opcode (unsigned long pc AU, /** 0110 0001 1111 1001 mov %e0, %1 */ ID(mov); DM2(HL, C, 0); SR(A); -/** 1100 1000 mov %0, #%1 */ +/** 1100 1000 mov %a0, #%1 */ ID(mov); DM(SP, IMMU(1)); SC(IMMU(1)); -/** 1001 1000 mov %0, %1 */ +/** 1001 1000 mov %a0, %1 */ ID(mov); DM(SP, IMMU(1)); SR(A); /** 1000 1111 mov %0, %e!1 */ @@ -662,7 +662,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 0110 0001 1110 1001 mov %0, %e1 */ ID(mov); DR(A); SM2(HL, C, 0); -/** 1000 1000 mov %0, %e1 */ +/** 1000 1000 mov %0, %ea1 */ ID(mov); DR(A); SM(SP, IMMU(1)); /** 0101 0reg mov %0, #%1 */ @@ -827,7 +827,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 1011 1100 movw %ea0, %1 */ ID(mov); W(); DM(HL, IMMU(1)); SR(AX); -/** 1011 1000 movw %0, %1 */ +/** 1011 1000 movw %a0, %1 */ ID(mov); W(); DM(SP, IMMU(1)); SR(AX); /** 1010 1111 movw %0, %e!1 */ @@ -846,7 +846,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 1010 1100 movw %0, %ea1 */ ID(mov); W(); DR(AX); SM(HL, IMMU(1)); -/** 1010 1000 movw %0, %1 */ +/** 1010 1000 movw %0, %a1 */ ID(mov); W(); DR(AX); SM(SP, IMMU(1)); /** 0011 0rg0 movw %0, #%1 */ |