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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-07-01 05:01:20 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-09-22 18:06:09 +0200 |
| commit | 6e17ae625570ff8f3c12c8765b8d45d4db8694bd (patch) | |
| tree | b2add49965e7e814881d5987f7c047a7756ea277 /opcodes/riscv-opc.c | |
| parent | 25236d63fdb138e24cb34aa6c513ae8de2dac7b8 (diff) | |
| download | gdb-6e17ae625570ff8f3c12c8765b8d45d4db8694bd.zip gdb-6e17ae625570ff8f3c12c8765b8d45d4db8694bd.tar.gz gdb-6e17ae625570ff8f3c12c8765b8d45d4db8694bd.tar.bz2 | |
RISC-V: Add T-Head MemPair vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemPair extension, a collection of T-Head specific
two-GP-register memory operations.
The 'th' prefix and the "XTheadMemPair" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'opcodes/riscv-opc.c')
| -rw-r--r-- | opcodes/riscv-opc.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 5aed98c..c1bcdb7 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -278,6 +278,23 @@ match_th_load_inc(const struct riscv_opcode *op, return rd != rs1 && match_opcode (op, insn); } +static int +match_th_load_pair(const struct riscv_opcode *op, + insn_t insn) +{ + /* Load pair instructions use the following encoding: + * - rd1 = RD (insn[11:7]) + * - rd2 = RS2 (insn[24:20]) + * - rs = RS1 ([19:15]) + * This function matches if the following restriction is met: + * The values of rd1, rd2, and rs1 must not be the same. */ + int rd1 = (insn & MASK_RD) >> OP_SH_RD; + int rd2 = (insn & MASK_RS2) >> OP_SH_RS2; + int rs = (insn & MASK_RS1) >> OP_SH_RS1; + + return rd1 != rd2 && rd1 != rs && rd2 != rs && match_opcode (op, insn); +} + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ @@ -1941,6 +1958,13 @@ const struct riscv_opcode riscv_opcodes[] = {"th.surh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURH, MASK_TH_SURH, match_opcode, 0}, {"th.surb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURB, MASK_TH_SURB, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadMemPair instructions. */ +{"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", MATCH_TH_LDD, MASK_TH_LDD, match_th_load_pair, 0}, +{"th.lwd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_LWD, MASK_TH_LWD, match_th_load_pair, 0}, +{"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, 0}, +{"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", MATCH_TH_SDD, MASK_TH_SDD, match_opcode, 0}, +{"th.swd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_SWD, MASK_TH_SWD, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadMac instructions. */ {"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0}, {"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0}, |