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| author | Jim Wilson <jimw@sifive.com> | 2019-02-08 12:57:12 -0800 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2019-02-08 13:16:50 -0800 |
| commit | ca0bc1509849a3871e99fdf48705b93f18d5fa7b (patch) | |
| tree | 843a43250dfbfecb21abe4c3ba215e37544a9983 /opcodes/riscv-opc.c | |
| parent | 46cbf38dc3a7c6d0e339f95d56590711b06427a1 (diff) | |
| download | gdb-ca0bc1509849a3871e99fdf48705b93f18d5fa7b.zip gdb-ca0bc1509849a3871e99fdf48705b93f18d5fa7b.tar.gz gdb-ca0bc1509849a3871e99fdf48705b93f18d5fa7b.tar.bz2 | |
RISC-V: Compress 3-operand beq/bne against x0.
This lets us accept an instruction like
beq a2,x0,.Label
and generate a compressed beqz. This will allow some future simplications
to the gcc support, e.g. eliminating some duplicate patterns, and avoiding
adding new duplicate patterns, since currently we have to handle signed
and equality compares against zero specially.
Tested with rv{32,64}-{elf,linux} cross builds and make checks for binutils
and gcc. There were no regressions.
gas/
* config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support.
(riscv_ip) <'C'>: Add 'z' support.
opcodes/
* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
<bne>: Likewise.
Diffstat (limited to 'opcodes/riscv-opc.c')
| -rw-r--r-- | opcodes/riscv-opc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 72e6b9d..bd65259 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -247,6 +247,7 @@ const struct riscv_opcode riscv_opcodes[] = {"and", 0, {"I", 0}, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS }, {"beqz", 0, {"C", 0}, "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"beqz", 0, {"I", 0}, "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, +{"beq", 0, {"C", 0}, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"beq", 0, {"I", 0}, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH }, {"blez", 0, {"I", 0}, "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bgez", 0, {"I", 0}, "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, @@ -262,6 +263,7 @@ const struct riscv_opcode riscv_opcodes[] = {"bgtu", 0, {"I", 0}, "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bnez", 0, {"C", 0}, "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bnez", 0, {"I", 0}, "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, +{"bne", 0, {"C", 0}, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bne", 0, {"I", 0}, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH }, {"addi", 0, {"C", 0}, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, {"addi", 0, {"C", 0}, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, |