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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-05-16 14:32:01 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-05-16 16:37:35 +0100 |
| commit | d3b6314397347943f40cdbf6efe34e209a162cc0 (patch) | |
| tree | 766fc65db88ab88965902ec73bb7fb8fbf71782b /opcodes/riscv-dis.c | |
| parent | 14925797f833c9f4eedab98c7c50961d180aa03f (diff) | |
| download | gdb-d3b6314397347943f40cdbf6efe34e209a162cc0.zip gdb-d3b6314397347943f40cdbf6efe34e209a162cc0.tar.gz gdb-d3b6314397347943f40cdbf6efe34e209a162cc0.tar.bz2 | |
[PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav, vmladav, vmlas, vrmlsldavh, vmlsldav, vmlsdav, vrmlaldavh, vqdmlah, vqrdmlash, vqrdmlash, vqdmlsdh, vqrdmlsdh, vqdmulh and vqrdmulh
opcodes/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_undefined): Add new reasons.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_undefined): Likewise.
(print_mve_size): Likewise.
(print_insn_mve): Likewise.
Diffstat (limited to 'opcodes/riscv-dis.c')
0 files changed, 0 insertions, 0 deletions