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authorKito Cheng <kito.cheng@gmail.com>2017-04-05 20:58:28 +0800
committerPalmer Dabbelt <palmer@dabbelt.com>2017-05-04 03:20:30 -0700
commitf91d48deb29d9e6f4b530f586db0140943ed0d83 (patch)
tree41c3e2ccd3bc4a9c346d80196851f94c6b220ef4 /opcodes/riscv-dis.c
parent45eba0ab7d26435121facb68847fbd0cd4a313c1 (diff)
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RISC-V: Fix disassemble for c.li, c.andi and c.addiw
ChangeLog 2017-05-03 Kito Cheng <kito.cheng@gmail.com> * riscv-dis.c (print_insn_args): Handle 'Co' operands.
Diffstat (limited to 'opcodes/riscv-dis.c')
-rw-r--r--opcodes/riscv-dis.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d760d70..bb53463 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
case 'i':
print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
break;
+ case 'o':
case 'j':
print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
break;