diff options
| author | Alan Modra <amodra@gmail.com> | 2017-03-17 19:06:12 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2017-03-17 19:09:15 +1030 |
| commit | 4b94dd2de12dd0389615700b13b63260e162ccf0 (patch) | |
| tree | 18ff7c121526b0440fdda095082adfa0bdb26f2b /opcodes/ppc-opc.c | |
| parent | 1d3fa25f5802fe2250f32f335ad57897a62e0fe2 (diff) | |
| download | gdb-4b94dd2de12dd0389615700b13b63260e162ccf0.zip gdb-4b94dd2de12dd0389615700b13b63260e162ccf0.tar.gz gdb-4b94dd2de12dd0389615700b13b63260e162ccf0.tar.bz2 | |
E6500 spr mnemonics
PR 21248
* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 3580453..7e9f9f4 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -5407,12 +5407,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}}, {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}}, {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}}, -{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}}, -{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, -{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}}, -{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, +{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE|E6500, 0, {RT}}, +{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE|E6500, 0, {RT}}, {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}}, {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}}, +{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, +{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}}, @@ -5760,12 +5760,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}}, {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}}, {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}}, -{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}}, -{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, -{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}}, -{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, +{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE|E6500, 0, {RS}}, +{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE|E6500, 0, {RS}}, {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}}, {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}}, +{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, +{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, |