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| author | Anton Blanchard <anton@samba.org> | 2015-09-22 15:39:24 +1000 |
|---|---|---|
| committer | Anton Blanchard <anton@samba.org> | 2015-09-22 16:10:14 +1000 |
| commit | 6dca4fd141fd0b9fe0ea662295833b8ed43cb4e8 (patch) | |
| tree | f6147950a00a9554608429e7859df8a052890acf /opcodes/ppc-opc.c | |
| parent | c8b187ea07f534bac147cbbc44dd08925f5734b0 (diff) | |
| download | gdb-6dca4fd141fd0b9fe0ea662295833b8ed43cb4e8.zip gdb-6dca4fd141fd0b9fe0ea662295833b8ed43cb4e8.tar.gz gdb-6dca4fd141fd0b9fe0ea662295833b8ed43cb4e8.tar.bz2 | |
opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics
opcodes/
* ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 66ab438..2526da4 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4878,6 +4878,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}}, {"mflr", XSPR(31,339, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}}, {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}}, +{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, PPCNONE, {RT}}, {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}}, {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, @@ -4893,6 +4894,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, PPCNONE, {RT}}, {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}}, {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}}, {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}}, @@ -5216,6 +5218,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, +{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, PPCNONE, {RS}}, {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}}, {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, @@ -5242,6 +5245,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}}, {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}}, {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, PPCNONE, {RS}}, {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}}, {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}}, {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}}, |