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| author | Alexander Fedotov <alfedotov@gmail.com> | 2017-09-30 12:31:37 +0300 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2017-10-01 19:35:06 +1030 |
| commit | d2e6c9a3682f0ac811ac1676d221c55162938b61 (patch) | |
| tree | 79eaa94ff6e6068274ed2908b3b625c3614f5d5d /opcodes/ppc-opc.c | |
| parent | 4b04bba2eb6b646e11a2c38c77667875b3db6828 (diff) | |
| download | gdb-d2e6c9a3682f0ac811ac1676d221c55162938b61.zip gdb-d2e6c9a3682f0ac811ac1676d221c55162938b61.tar.gz gdb-d2e6c9a3682f0ac811ac1676d221c55162938b61.tar.bz2 | |
Add new mnemonics for VLE multiple load instructions
opcodes/
* ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
VLE multimple load/store instructions. Old e_ldm* variants are
kept as aliases.
Add missing e_lmvmcsrrw and e_stmvmcsrrw.
gas/
* testsuite/gas/ppc/vle-mult-ld-st-insns.s: New file: Tests the
support for the VLE multiple load/store instructions.
* testsuite/gas/ppc/vle-mult-ld-st-insns.d: New file: Test
driver.
* testsuite/gas/ppc/ppc.exp: Run it.
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 5edb1ad..39f320a 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -8315,16 +8315,23 @@ const struct powerpc_opcode vle_opcodes[] = { {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, +{"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, +{"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, +{"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, +{"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, +{"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, +{"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, +{"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}}, |