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| author | Ben Elliston <bje@au.ibm.com> | 2004-04-30 06:46:53 +0000 |
|---|---|---|
| committer | Ben Elliston <bje@au.ibm.com> | 2004-04-30 06:46:53 +0000 |
| commit | f3806e43d9c7e6ff84ac5245e37ed21827783f4c (patch) | |
| tree | 2d0d14602238aae8b4f06d32575e59aff0990a4a /opcodes/ppc-opc.c | |
| parent | f7458fc96abdd1f9b2e5d2bc06a611210b60d60c (diff) | |
| download | gdb-f3806e43d9c7e6ff84ac5245e37ed21827783f4c.zip gdb-f3806e43d9c7e6ff84ac5245e37ed21827783f4c.tar.gz gdb-f3806e43d9c7e6ff84ac5245e37ed21827783f4c.tar.bz2 | |
* ppc-opc.c (powerpc_opcodes): Add "dbczl" instruction for PPC970.
[testsuite]
* gas/ppc/power4.s: Add dcbz and dcbzl test cases.
* gas/ppc/power4.d: Update accordingly.
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 36fe454..e9df5de 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -1585,15 +1585,14 @@ extract_tbr (unsigned long insn, /* An XRTRA_MASK, but with L bit clear. */ #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) -/* An X form comparison instruction. */ -#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) +/* An X form instruction with the L bit specified. */ +#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) /* The mask for an X form comparison instruction. */ #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) -/* The mask for an X form comparison instruction with the L field - fixed. */ -#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) +/* The mask for an X form instruction with the L field fixed. */ +#define XOPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) /* An X form trap instruction with the TO field specified. */ #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) @@ -3146,10 +3145,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, -{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, -{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, +{ "cmpw", XOPL(31,0,0), XOPL_MASK, PPCCOM, { OBF, RA, RB } }, +{ "cmpd", XOPL(31,0,1), XOPL_MASK, PPC64, { OBF, RA, RB } }, { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, -{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, +{ "cmp", X(31,0), XOPL_MASK, PWRCOM, { BF, RA, RB } }, { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, @@ -3252,10 +3251,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } }, -{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, -{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, +{ "cmplw", XOPL(31,32,0), XOPL_MASK, PPCCOM, { OBF, RA, RB } }, +{ "cmpld", XOPL(31,32,1), XOPL_MASK, PPC64, { OBF, RA, RB } }, { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, -{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, +{ "cmpl", X(31,32), XOPL_MASK, PWRCOM, { BF, RA, RB } }, { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, @@ -4303,6 +4302,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, +{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } }, { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, |