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| author | Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> | 2014-07-20 20:26:09 +0300 |
|---|---|---|
| committer | Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> | 2014-07-20 20:26:09 +0300 |
| commit | 018dc9bedf40d528f1d05d56555e20ed54a77dc3 (patch) | |
| tree | 3b00411c0efdc5c37291f60739bf6f28ea3c5980 /opcodes/or1k-desc.c | |
| parent | 164224e96ca270d6cbb61d3e326fc1b0453b30a6 (diff) | |
| download | gdb-018dc9bedf40d528f1d05d56555e20ed54a77dc3.zip gdb-018dc9bedf40d528f1d05d56555e20ed54a77dc3.tar.gz gdb-018dc9bedf40d528f1d05d56555e20ed54a77dc3.tar.bz2 | |
or1k: add missing l.msync, l.psync and l.psync instructions.
Even though the opcodes were defined for these instructions,
the actual instruction definitions were lacking.
cpu/
* or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.
opcodes/
* or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
* or1k-opinst.c: Regenerate.
Diffstat (limited to 'opcodes/or1k-desc.c')
| -rw-r--r-- | opcodes/or1k-desc.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/opcodes/or1k-desc.c b/opcodes/or1k-desc.c index 84b0c81..b5174a0 100644 --- a/opcodes/or1k-desc.c +++ b/opcodes/or1k-desc.c @@ -952,6 +952,7 @@ const CGEN_IFLD or1k_cgen_ifld_table[] = { OR1K_F_RESV_25_10, "f-resv-25-10", 0, 32, 25, 10, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, { OR1K_F_RESV_25_5, "f-resv-25-5", 0, 32, 25, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, { OR1K_F_RESV_23_8, "f-resv-23-8", 0, 32, 23, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, + { OR1K_F_RESV_20_21, "f-resv-20-21", 0, 32, 20, 21, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, { OR1K_F_RESV_20_5, "f-resv-20-5", 0, 32, 20, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, { OR1K_F_RESV_20_4, "f-resv-20-4", 0, 32, 20, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, { OR1K_F_RESV_15_8, "f-resv-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, @@ -1189,6 +1190,21 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] = OR1K_INSN_L_SYS, "l-sys", "l.sys", 32, { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } }, +/* l.msync */ + { + OR1K_INSN_L_MSYNC, "l-msync", "l.msync", 32, + { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } + }, +/* l.psync */ + { + OR1K_INSN_L_PSYNC, "l-psync", "l.psync", 32, + { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } + }, +/* l.csync */ + { + OR1K_INSN_L_CSYNC, "l-csync", "l.csync", 32, + { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } + }, /* l.rfe */ { OR1K_INSN_L_RFE, "l-rfe", "l.rfe", 32, |