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authorNathan Sidwell <nathan@codesourcery.com>2005-11-08 11:15:13 +0000
committerNathan Sidwell <nathan@codesourcery.com>2005-11-08 11:15:13 +0000
commit6f84a2a6497dab3564cb0fb0031632700158393b (patch)
treee2f6f244e27b5cc4d4c0e1ed433776221a7d12c5 /opcodes/ms1-ibld.c
parent16ac4ab5a8d7c4998e8a2648a452df6e96e5e4ef (diff)
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bfd:
Add ms2. * archures.c (bfd_mach_ms2): Define. * cpu-ms1.c (arch_info_struct): Add ms2 stanza. * elf32-ms1.c (elf32_ms1_machine): Add ms2 case. (ms1_elf_merge_private_bfd_data): Remove unused variables. Add correct merging logic, with workaround. (ms1_elf_print_private_bfd_data): Add ms2 case. * reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc. * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. cpu: Add ms2 * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and model. (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr, f-cb2incr, f-rc3): New fields. (LOOP): New instruction. (JAL-HAZARD): New hazard. (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr): New operands. (mul, muli, dbnz, iflush): Enable for ms2 (jal, reti): Has JAL-HAZARD. (ldctxt, ldfb, stfb): Only ms1. (fbcb): Only ms1,ms1-003. (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs, fbcbincrs, mfbcbincrs): Enable for ms2. (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns. * ms1.opc (parse_loopsize): New. (parse_imm16): hi16/lo16 relocs are applicable to IMM16L. (print_pcrel): New. gas: Add ms2. * config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1. (ms1_architectures): Add ms2. (md_parse_option): Add ms2. (md_show_usage): Add ms2. (md_assemble): Add JAL_HAZARD detection logic. (md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case. * doc/c-ms1.texi: New. * doc/all.texi: Add MS1. * doc/Makefile.am (CPU_DOCS): Add c-ms1.texi. * doc/Makefile.in: Rebuilt. * doc/Makefile: Rebuilt. gas/testsuite: Add ms2. * gas/ms1/allinsn.d: Adjust pcrel disassembly. * gas/ms1/errors.exp: Fix target triplet. * gas/ms1/ms1-16-003.d: Adjust pcrel disassembly. * gas/ms1/ms1-16-003.s: Tweak label. * gas/ms1/ms1.exp: Adjust target triplet. Add ms2 test. * gas/ms1/ms2.d, gas/ms1/ms2.s: New. * gas/ms1/relocs.d: Adjust expected machine name and pcrel disassembly. * gas/ms1/relocs.exp: Adjust target triplet. include: Add ms2. * elf/ms1.h (EF_MS1_CPU_MS2): New. opcodes: Add ms2. * ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h: Regenerated.
Diffstat (limited to 'opcodes/ms1-ibld.c')
-rw-r--r--opcodes/ms1-ibld.c135
1 files changed, 135 insertions, 0 deletions
diff --git a/opcodes/ms1-ibld.c b/opcodes/ms1-ibld.c
index 3ffbd84..4640211 100644
--- a/opcodes/ms1-ibld.c
+++ b/opcodes/ms1-ibld.c
@@ -576,6 +576,18 @@ ms1_cgen_insert_operand (CGEN_CPU_DESC cd,
case MS1_OPERAND_BRC2 :
errmsg = insert_normal (cd, fields->f_brc2, 0, 0, 14, 3, 32, total_length, buffer);
break;
+ case MS1_OPERAND_CB1INCR :
+ errmsg = insert_normal (cd, fields->f_cb1incr, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 6, 32, total_length, buffer);
+ break;
+ case MS1_OPERAND_CB1SEL :
+ errmsg = insert_normal (cd, fields->f_cb1sel, 0, 0, 25, 3, 32, total_length, buffer);
+ break;
+ case MS1_OPERAND_CB2INCR :
+ errmsg = insert_normal (cd, fields->f_cb2incr, 0|(1<<CGEN_IFLD_SIGNED), 0, 13, 6, 32, total_length, buffer);
+ break;
+ case MS1_OPERAND_CB2SEL :
+ errmsg = insert_normal (cd, fields->f_cb2sel, 0, 0, 22, 3, 32, total_length, buffer);
+ break;
case MS1_OPERAND_CBRB :
errmsg = insert_normal (cd, fields->f_cbrb, 0, 0, 10, 1, 32, total_length, buffer);
break;
@@ -637,6 +649,9 @@ ms1_cgen_insert_operand (CGEN_CPU_DESC cd,
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer);
}
break;
+ case MS1_OPERAND_IMM16L :
+ errmsg = insert_normal (cd, fields->f_imm16l, 0, 0, 23, 16, 32, total_length, buffer);
+ break;
case MS1_OPERAND_IMM16O :
{
long value = fields->f_imm16s;
@@ -656,6 +671,13 @@ ms1_cgen_insert_operand (CGEN_CPU_DESC cd,
case MS1_OPERAND_LENGTH :
errmsg = insert_normal (cd, fields->f_length, 0, 0, 15, 3, 32, total_length, buffer);
break;
+ case MS1_OPERAND_LOOPSIZE :
+ {
+ long value = fields->f_loopo;
+ value = ((unsigned int) (value) >> (2));
+ errmsg = insert_normal (cd, value, 0, 0, 7, 8, 32, total_length, buffer);
+ }
+ break;
case MS1_OPERAND_MASK :
errmsg = insert_normal (cd, fields->f_mask, 0, 0, 25, 16, 32, total_length, buffer);
break;
@@ -680,6 +702,9 @@ ms1_cgen_insert_operand (CGEN_CPU_DESC cd,
case MS1_OPERAND_RC2 :
errmsg = insert_normal (cd, fields->f_rc2, 0, 0, 6, 1, 32, total_length, buffer);
break;
+ case MS1_OPERAND_RC3 :
+ errmsg = insert_normal (cd, fields->f_rc3, 0, 0, 7, 1, 32, total_length, buffer);
+ break;
case MS1_OPERAND_RCNUM :
errmsg = insert_normal (cd, fields->f_rcnum, 0, 0, 14, 3, 32, total_length, buffer);
break;
@@ -768,6 +793,18 @@ ms1_cgen_extract_operand (CGEN_CPU_DESC cd,
case MS1_OPERAND_BRC2 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_brc2);
break;
+ case MS1_OPERAND_CB1INCR :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 6, 32, total_length, pc, & fields->f_cb1incr);
+ break;
+ case MS1_OPERAND_CB1SEL :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_cb1sel);
+ break;
+ case MS1_OPERAND_CB2INCR :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 13, 6, 32, total_length, pc, & fields->f_cb2incr);
+ break;
+ case MS1_OPERAND_CB2SEL :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_cb2sel);
+ break;
case MS1_OPERAND_CBRB :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_cbrb);
break;
@@ -830,6 +867,9 @@ ms1_cgen_extract_operand (CGEN_CPU_DESC cd,
fields->f_imm16s = value;
}
break;
+ case MS1_OPERAND_IMM16L :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 16, 32, total_length, pc, & fields->f_imm16l);
+ break;
case MS1_OPERAND_IMM16O :
{
long value;
@@ -850,6 +890,14 @@ ms1_cgen_extract_operand (CGEN_CPU_DESC cd,
case MS1_OPERAND_LENGTH :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_length);
break;
+ case MS1_OPERAND_LOOPSIZE :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & value);
+ value = ((((value) << (2))) + (8));
+ fields->f_loopo = value;
+ }
+ break;
case MS1_OPERAND_MASK :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 16, 32, total_length, pc, & fields->f_mask);
break;
@@ -874,6 +922,9 @@ ms1_cgen_extract_operand (CGEN_CPU_DESC cd,
case MS1_OPERAND_RC2 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_rc2);
break;
+ case MS1_OPERAND_RC3 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_rc3);
+ break;
case MS1_OPERAND_RCNUM :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_rcnum);
break;
@@ -957,6 +1008,18 @@ ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_BRC2 :
value = fields->f_brc2;
break;
+ case MS1_OPERAND_CB1INCR :
+ value = fields->f_cb1incr;
+ break;
+ case MS1_OPERAND_CB1SEL :
+ value = fields->f_cb1sel;
+ break;
+ case MS1_OPERAND_CB2INCR :
+ value = fields->f_cb2incr;
+ break;
+ case MS1_OPERAND_CB2SEL :
+ value = fields->f_cb2sel;
+ break;
case MS1_OPERAND_CBRB :
value = fields->f_cbrb;
break;
@@ -1014,6 +1077,9 @@ ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_IMM16 :
value = fields->f_imm16s;
break;
+ case MS1_OPERAND_IMM16L :
+ value = fields->f_imm16l;
+ break;
case MS1_OPERAND_IMM16O :
value = fields->f_imm16s;
break;
@@ -1029,6 +1095,9 @@ ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_LENGTH :
value = fields->f_length;
break;
+ case MS1_OPERAND_LOOPSIZE :
+ value = fields->f_loopo;
+ break;
case MS1_OPERAND_MASK :
value = fields->f_mask;
break;
@@ -1053,6 +1122,9 @@ ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_RC2 :
value = fields->f_rc2;
break;
+ case MS1_OPERAND_RC3 :
+ value = fields->f_rc3;
+ break;
case MS1_OPERAND_RCNUM :
value = fields->f_rcnum;
break;
@@ -1118,6 +1190,18 @@ ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_BRC2 :
value = fields->f_brc2;
break;
+ case MS1_OPERAND_CB1INCR :
+ value = fields->f_cb1incr;
+ break;
+ case MS1_OPERAND_CB1SEL :
+ value = fields->f_cb1sel;
+ break;
+ case MS1_OPERAND_CB2INCR :
+ value = fields->f_cb2incr;
+ break;
+ case MS1_OPERAND_CB2SEL :
+ value = fields->f_cb2sel;
+ break;
case MS1_OPERAND_CBRB :
value = fields->f_cbrb;
break;
@@ -1175,6 +1259,9 @@ ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_IMM16 :
value = fields->f_imm16s;
break;
+ case MS1_OPERAND_IMM16L :
+ value = fields->f_imm16l;
+ break;
case MS1_OPERAND_IMM16O :
value = fields->f_imm16s;
break;
@@ -1190,6 +1277,9 @@ ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_LENGTH :
value = fields->f_length;
break;
+ case MS1_OPERAND_LOOPSIZE :
+ value = fields->f_loopo;
+ break;
case MS1_OPERAND_MASK :
value = fields->f_mask;
break;
@@ -1214,6 +1304,9 @@ ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_RC2 :
value = fields->f_rc2;
break;
+ case MS1_OPERAND_RC3 :
+ value = fields->f_rc3;
+ break;
case MS1_OPERAND_RCNUM :
value = fields->f_rcnum;
break;
@@ -1286,6 +1379,18 @@ ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_BRC2 :
fields->f_brc2 = value;
break;
+ case MS1_OPERAND_CB1INCR :
+ fields->f_cb1incr = value;
+ break;
+ case MS1_OPERAND_CB1SEL :
+ fields->f_cb1sel = value;
+ break;
+ case MS1_OPERAND_CB2INCR :
+ fields->f_cb2incr = value;
+ break;
+ case MS1_OPERAND_CB2SEL :
+ fields->f_cb2sel = value;
+ break;
case MS1_OPERAND_CBRB :
fields->f_cbrb = value;
break;
@@ -1343,6 +1448,9 @@ ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_IMM16 :
fields->f_imm16s = value;
break;
+ case MS1_OPERAND_IMM16L :
+ fields->f_imm16l = value;
+ break;
case MS1_OPERAND_IMM16O :
fields->f_imm16s = value;
break;
@@ -1358,6 +1466,9 @@ ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_LENGTH :
fields->f_length = value;
break;
+ case MS1_OPERAND_LOOPSIZE :
+ fields->f_loopo = value;
+ break;
case MS1_OPERAND_MASK :
fields->f_mask = value;
break;
@@ -1382,6 +1493,9 @@ ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_RC2 :
fields->f_rc2 = value;
break;
+ case MS1_OPERAND_RC3 :
+ fields->f_rc3 = value;
+ break;
case MS1_OPERAND_RCNUM :
fields->f_rcnum = value;
break;
@@ -1444,6 +1558,18 @@ ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_BRC2 :
fields->f_brc2 = value;
break;
+ case MS1_OPERAND_CB1INCR :
+ fields->f_cb1incr = value;
+ break;
+ case MS1_OPERAND_CB1SEL :
+ fields->f_cb1sel = value;
+ break;
+ case MS1_OPERAND_CB2INCR :
+ fields->f_cb2incr = value;
+ break;
+ case MS1_OPERAND_CB2SEL :
+ fields->f_cb2sel = value;
+ break;
case MS1_OPERAND_CBRB :
fields->f_cbrb = value;
break;
@@ -1501,6 +1627,9 @@ ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_IMM16 :
fields->f_imm16s = value;
break;
+ case MS1_OPERAND_IMM16L :
+ fields->f_imm16l = value;
+ break;
case MS1_OPERAND_IMM16O :
fields->f_imm16s = value;
break;
@@ -1516,6 +1645,9 @@ ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_LENGTH :
fields->f_length = value;
break;
+ case MS1_OPERAND_LOOPSIZE :
+ fields->f_loopo = value;
+ break;
case MS1_OPERAND_MASK :
fields->f_mask = value;
break;
@@ -1540,6 +1672,9 @@ ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MS1_OPERAND_RC2 :
fields->f_rc2 = value;
break;
+ case MS1_OPERAND_RC3 :
+ fields->f_rc3 = value;
+ break;
case MS1_OPERAND_RCNUM :
fields->f_rcnum = value;
break;