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| author | Maciej W. Rozycki <macro@imgtec.com> | 2017-04-25 11:44:29 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-04-25 11:55:34 +0100 |
| commit | 6e3d1f0728d980a384c5aa63ce7f2ff3919c5024 (patch) | |
| tree | 131f83b92152d6710c91c9112b8cc07252438c58 /opcodes/mips16-opc.c | |
| parent | adc1273cb27286452ed8b32c5ca3ea263b4854f0 (diff) | |
| download | gdb-6e3d1f0728d980a384c5aa63ce7f2ff3919c5024.zip gdb-6e3d1f0728d980a384c5aa63ce7f2ff3919c5024.tar.gz gdb-6e3d1f0728d980a384c5aa63ce7f2ff3919c5024.tar.bz2 | |
MIPS16/opcodes: Annotate instruction aliases
Complement commit 986e18a5a9fd ("Add a second 'pinfo' member to
mips_opcode to extend number of available bits"),
<https://sourceware.org/ml/binutils/2005-01/msg00261.html>, and annotate
MIPS16 NOP, LA, DLA and the synthetic forms of LD and LW instructions as
aliases. These correspond to MOVE, and the PC-relative ADDIU, DADDIU,
LD and LW hardware instructions respectively.
binutils/
* testsuite/binutils-all/mips/mips16-alias.d: New test.
* testsuite/binutils-all/mips/mips16-noalias.d: New test.
* testsuite/binutils-all/mips/mips16-alias.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
opcodes/
* mips16-opc.c (AL): New macro.
(mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
of "ld" and "lw" as aliases.
Diffstat (limited to 'opcodes/mips16-opc.c')
| -rw-r--r-- | opcodes/mips16-opc.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c index 96746d8..7c8a0be 100644 --- a/opcodes/mips16-opc.c +++ b/opcodes/mips16-opc.c @@ -145,6 +145,8 @@ decode_mips16_operand (char type, bfd_boolean extended_p) /* Use some short hand macros to keep down the length of the lines in the opcodes table. */ +#define AL INSN2_ALIAS + #define UBD INSN_UNCOND_BRANCH_DELAY #define WR_1 INSN_WRITE_1 @@ -188,8 +190,8 @@ decode_mips16_operand (char type, bfd_boolean extended_p) const struct mips_opcode mips16_opcodes[] = { /* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */ -{"nop", "", 0x6500, 0xffff, 0, SH|RD_16, I1, 0, 0 }, /* move $0,$Z */ -{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, +{"nop", "", 0x6500, 0xffff, 0, SH|RD_16|AL, I1, 0, 0 }, /* move $0,$Z */ +{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 }, {"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, {"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 }, {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, @@ -234,7 +236,7 @@ const struct mips_opcode mips16_opcodes[] = {"cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, {"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 }, {"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, -{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, +{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 }, {"daddiu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 }, {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, {"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, @@ -301,14 +303,14 @@ const struct mips_opcode mips16_opcodes[] = {"lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, {"lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, {"ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 }, -{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, +{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 }, {"ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, {"ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 }, {"lh", "y,H(x)", 0x8800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, {"lhu", "y,H(x)", 0xa800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, {"li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 }, {"lw", "y,W(x)", 0x9800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, -{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 }, +{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 }, {"lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 }, {"lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, {"lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 }, |