* mips-opc.c: Added r6000 and r4000 instructions and macros.

	Changed hazard information to distinguish between memory load
	delays and coprocessor load delays.

1 files changed, 212 insertions, 26 deletions

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index c49d1fc..0172695 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -25,16 +25,20 @@ Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
 
 /* Short hand so the lines aren't too long.  */
 
-#define LDD     INSN_LOAD_DELAY
+#define LDD     INSN_LOAD_MEMORY_DELAY
+#define LCD	INSN_LOAD_COPROC_DELAY
 #define UBD     INSN_UNCOND_BRANCH_DELAY
 #define CBD	INSN_COND_BRANCH_DELAY
-#define COD     INSN_COPROC_DELAY
+#define COD     INSN_COPROC_MOVE_DELAY
+#define CLD	INSN_COPROC_MEMORY_DELAY
+#define CBL	INSN_COND_BRANCH_LIKELY
 
 #define WR_d    INSN_WRITE_GPR_D
 #define WR_t    INSN_WRITE_GPR_T
 #define WR_31   INSN_WRITE_GPR_31       
 #define WR_D    INSN_WRITE_FPR_D        
 #define WR_T	INSN_WRITE_FPR_T
+#define WR_S	INSN_WRITE_FPR_S
 #define RD_s    INSN_READ_GPR_S         
 #define RD_b    INSN_READ_GPR_S         
 #define RD_t    INSN_READ_GPR_T         
@@ -55,6 +59,9 @@ Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
 #define RD_HI	INSN_READ_HI
 #define RD_LO	INSN_READ_LO
 
+#define I2	INSN_ISA2
+#define I3	INSN_ISA3
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -96,41 +103,77 @@ const struct mips_opcode mips_opcodes[] = {
 /* b is at the top of the table.  */
 /* bal is at the top of the table.  */
 {"bc0f",    "p",	0x41000000, 0xffff0000,	CBD|RD_CC	},
+{"bc0fl",   "p",	0x41020000, 0xffff0000,	CBL|RD_CC|I2	},
 {"bc1f",    "p",	0x45000000, 0xffff0000,	CBD|RD_CC	},
+{"bc1fl",   "p",	0x45020000, 0xffff0000,	CBL|RD_CC|I2	},
 {"bc2f",    "p",	0x49000000, 0xffff0000,	CBD|RD_CC	},
+{"bc2fl",   "p",	0x49020000, 0xffff0000,	CBL|RD_CC|I2	},
 {"bc3f",    "p",	0x4d000000, 0xffff0000,	CBD|RD_CC	},
+{"bc3fl",   "p",	0x4d020000, 0xffff0000,	CBL|RD_CC|I2	},
 {"bc0t",    "p",	0x41010000, 0xffff0000,	CBD|RD_CC	},
+{"bc0tl",   "p",	0x41030000, 0xffff0000,	CBL|RD_CC|I2	},
 {"bc1t",    "p",	0x45010000, 0xffff0000,	CBD|RD_CC	},
+{"bc1tl",   "p",	0x45030000, 0xffff0000,	CBL|RD_CC|I2	},
 {"bc2t",    "p",	0x49010000, 0xffff0000,	CBD|RD_CC	},
+{"bc2tl",   "p",	0x49030000, 0xffff0000,	CBL|RD_CC|I2	},
 {"bc3t",    "p",	0x4d010000, 0xffff0000,	CBD|RD_CC	},
+{"bc3tl",   "p",	0x4d030000, 0xffff0000,	CBL|RD_CC|I2	},
+{"beqz",    "s,p",	0x10000000, 0xfc1f0000,	CBD|RD_s	},
+{"beqzl",   "s,p",	0x50000000, 0xfc1f0000,	CBD|RD_s|I2	},
 {"beq",     "s,t,p",	0x10000000, 0xfc000000,	CBD|RD_s|RD_t	},
 {"beq",     "s,I,p",	0,    (int) M_BEQ_I,	INSN_MACRO	},
-{"beqz",    "s,p",	0x10000000, 0xfc1f0000,	CBD|RD_s	},
+{"beql",    "s,t,p",	0x50000000, 0xfc000000,	CBL|RD_s|RD_t|I2},
+{"beql",    "s,I,p",	2,    (int) M_BEQL_I,	INSN_MACRO	},
 {"bge",     "s,t,p",	0,    (int) M_BGE,	INSN_MACRO	},
 {"bge",     "s,I,p",	0,    (int) M_BGE_I,	INSN_MACRO	},
+{"bgel",    "s,t,p",	2,    (int) M_BGEL,	INSN_MACRO	},
+{"bgel",    "s,I,p",	2,    (int) M_BGEL_I,	INSN_MACRO	},
 {"bgeu",    "s,t,p",	0,    (int) M_BGEU,	INSN_MACRO	},
 {"bgeu",    "s,I,p",	0,    (int) M_BGEU_I,	INSN_MACRO	},
+{"bgeul",   "s,t,p",	2,    (int) M_BGEUL,	INSN_MACRO	},
+{"bgeul",   "s,I,p",	2,    (int) M_BGEUL_I,	INSN_MACRO	},
 {"bgez",    "s,p",	0x04010000, 0xfc1f0000,	CBD|RD_s	},
+{"bgezl",   "s,p",	0x04030000, 0xfc1f0000,	CBD|RD_s|I2	},
 {"bgezal",  "s,p",	0x04110000, 0xfc1f0000,	CBD|RD_s	},
+{"bgezall", "s,p",	0x04130000, 0xfc1f0000,	CBD|RD_s|I2	},
 {"bgt",     "s,t,p",	0,    (int) M_BGT,	INSN_MACRO	},
 {"bgt",     "s,I,p",	0,    (int) M_BGT_I,	INSN_MACRO	},
+{"bgtl",    "s,t,p",	2,    (int) M_BGTL,	INSN_MACRO	},
+{"bgtl",    "s,I,p",	2,    (int) M_BGTL_I,	INSN_MACRO	},
 {"bgtu",    "s,t,p",	0,    (int) M_BGTU,	INSN_MACRO	},
 {"bgtu",    "s,I,p",	0,    (int) M_BGTU_I,	INSN_MACRO	},
+{"bgtul",   "s,t,p",	2,    (int) M_BGTUL,	INSN_MACRO	},
+{"bgtul",   "s,I,p",	2,    (int) M_BGTUL_I,	INSN_MACRO	},
 {"bgtz",    "s,p",	0x1c000000, 0xfc1f0000,	CBD|RD_s	},
+{"bgtzl",   "s,p",	0x5c000000, 0xfc1f0000,	CBD|RD_s|I2	},
 {"ble",     "s,t,p",	0,    (int) M_BLE,	INSN_MACRO	},
 {"ble",     "s,I,p",	0,    (int) M_BLE_I,	INSN_MACRO	},
+{"blel",    "s,t,p",	2,    (int) M_BLEL,	INSN_MACRO	},
+{"blel",    "s,I,p",	2,    (int) M_BLEL_I,	INSN_MACRO	},
 {"bleu",    "s,t,p",	0,    (int) M_BLEU,	INSN_MACRO	},
 {"bleu",    "s,I,p",	0,    (int) M_BLEU_I,	INSN_MACRO	},
+{"bleul",   "s,t,p",	2,    (int) M_BLEUL,	INSN_MACRO	},
+{"bleul",   "s,I,p",	2,    (int) M_BLEUL_I,	INSN_MACRO	},
 {"blez",    "s,p",	0x18000000, 0xfc1f0000,	CBD|RD_s	},
+{"blezl",   "s,p",	0x58000000, 0xfc1f0000,	CBD|RD_s|I2	},
 {"blt",     "s,t,p",	0,    (int) M_BLT,	INSN_MACRO	},
 {"blt",     "s,I,p",	0,    (int) M_BLT_I,	INSN_MACRO	},
+{"bltl",    "s,t,p",	2,    (int) M_BLTL,	INSN_MACRO	},
+{"bltl",    "s,I,p",	2,    (int) M_BLTL_I,	INSN_MACRO	},
 {"bltu",    "s,t,p",	0,    (int) M_BLTU,	INSN_MACRO	},
 {"bltu",    "s,I,p",	0,    (int) M_BLTU_I,	INSN_MACRO	},
+{"bltul",   "s,t,p",	2,    (int) M_BLTUL,	INSN_MACRO	},
+{"bltul",   "s,I,p",	2,    (int) M_BLTUL_I,	INSN_MACRO	},
 {"bltz",    "s,p",	0x04000000, 0xfc1f0000,	CBD|RD_s	},
+{"bltzl",   "s,p",	0x04020000, 0xfc1f0000,	CBD|RD_s|I2	},
 {"bltzal",  "s,p",	0x04100000, 0xfc1f0000,	CBD|RD_s	},
+{"bltzall", "s,p",	0x04120000, 0xfc1f0000,	CBD|RD_s|I2	},
+{"bnez",    "s,p",	0x14000000, 0xfc1f0000,	CBD|RD_s	},
+{"bnezl",   "s,p",	0x54000000, 0xfc1f0000,	CBD|RD_s|I2	},
 {"bne",     "s,t,p",	0x14000000, 0xfc000000,	CBD|RD_s|RD_t	},
 {"bne",     "s,I,p",	0,    (int) M_BNE_I,	INSN_MACRO	},
-{"bnez",    "s,p",	0x14000000, 0xfc1f0000,	CBD|RD_s	},
+{"bnel",    "s,t,p",	0x54000000, 0xfc000000,	CBD|RD_s|RD_t	},
+{"bnel",    "s,I,p",	2,    (int) M_BNEL_I,	INSN_MACRO	},
 {"break",   "",		0x0000000d, 0xffffffff,	INSN_TRAP	},
 {"break",   "c",	0x0000000d, 0xfc00003f,	INSN_TRAP	},
 {"c.f.d",   "S,T",	0x46200030, 0xffe007ff,	RD_S|RD_T|WR_CC	},
@@ -165,23 +208,44 @@ const struct mips_opcode mips_opcodes[] = {
 {"c.le.s",  "S,T",	0x4600003e, 0xffe007ff,	RD_S|RD_T|WR_CC	},
 {"c.ngt.d", "S,T",	0x4620003f, 0xffe007ff,	RD_S|RD_T|WR_CC	},
 {"c.ngt.s", "S,T",	0x4600003f, 0xffe007ff,	RD_S|RD_T|WR_CC	},
-{"cfc0",    "t,G",	0x40400000, 0xffe007ff,	LDD|WR_t|RD_C0	},
-{"cfc1",    "t,G",	0x44400000, 0xffe007ff,	LDD|WR_t|RD_C1	},
-{"cfc1",    "t,S",	0x44400000, 0xffe007ff,	LDD|WR_t|RD_C1	},
-{"cfc2",    "t,G",	0x48400000, 0xffe007ff,	LDD|WR_t|RD_C2	},
-{"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LDD|WR_t|RD_C3	},
+{"cache",   "t,o(b)",	0xbc000000, 0xfc000000, RD_b|I3		},
+{"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|I3	},
+{"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|I3	},
+{"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|I2	},
+{"ceil.w.s", "D,S",	0x4600000e, 0xffff003f, WR_D|RD_S|I2	},
+{"cfc0",    "t,G",	0x40400000, 0xffe007ff,	LCD|WR_t|RD_C0	},
+{"cfc1",    "t,G",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1	},
+{"cfc1",    "t,S",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1	},
+{"cfc2",    "t,G",	0x48400000, 0xffe007ff,	LCD|WR_t|RD_C2	},
+{"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LCD|WR_t|RD_C3	},
 {"ctc0",    "t,G",	0x40c00000, 0xffe007ff,	COD|RD_t|WR_CC	},
 {"ctc1",    "t,G",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC	},
 {"ctc1",    "t,S",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC	},
 {"ctc2",    "t,G",	0x48c00000, 0xffe007ff,	COD|RD_t|WR_CC	},
 {"ctc3",    "t,G",	0x4cc00000, 0xffe007ff,	COD|RD_t|WR_CC	},
+{"cvt.d.l", "D,S",	0x46a00021, 0xffff003f,	WR_D|RD_S|I3	},
 {"cvt.d.s", "D,S",	0x46000021, 0xffff003f,	WR_D|RD_S	},
 {"cvt.d.w", "D,S",	0x46800021, 0xffff003f,	WR_D|RD_S	},
+{"cvt.l.d", "D,S",	0x46200025, 0xffff003f,	WR_D|RD_S|I3	},
+{"cvt.l.s", "D,S",	0x46000025, 0xffff003f,	WR_D|RD_S|I3	},
+{"cvt.s.l", "D,S",	0x46a00020, 0xffff003f,	WR_D|RD_S|I3	},
 {"cvt.s.d", "D,S",	0x46200020, 0xffff003f,	WR_D|RD_S	},
 {"cvt.s.w", "D,S",	0x46800020, 0xffff003f,	WR_D|RD_S	},
 {"cvt.w.d", "D,S",	0x46200024, 0xffff003f,	WR_D|RD_S	},
 {"cvt.w.s", "D,S",	0x46000024, 0xffff003f,	WR_D|RD_S	},
-{"div",     "s,t",	0x0000001a, 0xfc00003f,	RD_s|RD_t|WR_HI|WR_LO	},
+{"dadd",    "d,v,t",	0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
+{"dadd",    "t,r,I",	3,    (int) M_DADD_I,	INSN_MACRO	},
+{"daddi",   "t,r,j",	0x60000000, 0xfc000000, WR_t|RD_s|I3	},
+{"daddiu",  "t,r,j",	0x64000000, 0xfc000000, WR_t|RD_s|I3	},
+{"daddu",   "d,v,t",	0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
+{"daddu",   "t,r,I",	3,    (int) M_DADDU_I,	INSN_MACRO	},
+{"ddiv",    "s,t",	0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
+{"ddiv",    "d,s,t",	3,    (int) M_DDIV_3,	INSN_MACRO	},
+{"ddiv",    "d,v,I",	3,    (int) M_DDIV_3I,	INSN_MACRO	},
+{"ddivu",   "s,t",	0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
+{"ddivu",   "d,s,t",	3,    (int) M_DDIVU_3,	INSN_MACRO	},
+{"ddivu",   "d,v,I",	3,    (int) M_DDIVU_3I,	INSN_MACRO	},
+{"div",     "s,t",	0x0000001a, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO	},
 {"div",     "d,s,t",	0,    (int) M_DIV_3,	INSN_MACRO	},
 {"div",     "d,v,I",	0,    (int) M_DIV_3I,	INSN_MACRO	},
 {"div.d",   "D,V,T",	0x46200003, 0xffe0003f,	WR_D|RD_S|RD_T	},
@@ -189,14 +253,54 @@ const struct mips_opcode mips_opcodes[] = {
 {"divu",    "s,t",	0x0000001b, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO	},
 {"divu",    "d,s,t",	0,    (int) M_DIVU_3,	INSN_MACRO	},
 {"divu",    "d,v,I",	0,    (int) M_DIVU_3I,	INSN_MACRO	},
+{"dmfc0",   "t,G",	0x40200000, 0xffe007ff, LCD|WR_t|RD_C0|I3 },
+{"dmtc0",   "t,G",	0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC|I3 },
+{"dmfc1",   "t,S",	0x44200000, 0xffe007ff, LCD|WR_t|RD_S|I3 },
+{"dmtc1",   "t,S",	0x44a00000, 0xffe007ff, COD|RD_t|WR_S|I3 },
+{"dmul",    "d,v,t",	3,    (int) M_DMUL,	INSN_MACRO	},
+{"dmul",    "d,v,I",	3,    (int) M_DMUL_I,	INSN_MACRO	},
+{"dmulo",   "d,v,t",	3,    (int) M_DMULO,	INSN_MACRO	},
+{"dmulo",   "d,v,I",	3,    (int) M_DMULO_I,	INSN_MACRO	},
+{"dmulou",  "d,v,t",	3,    (int) M_DMULOU,	INSN_MACRO	},
+{"dmulou",  "d,v,I",	3,    (int) M_DMULOU_I,	INSN_MACRO	},
+{"dmult",   "s,t",	0x0000001c, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|I3 },
+{"dmultu",  "s,t",	0x0000001d, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|I3 },
+{"dneg",    "d,w",	0x0000002e, 0xffe007ff,	WR_d|RD_t|I3	}, /* dsub 0 */
+{"dnegu",   "d,w",	0x0000002f, 0xffe007ff,	WR_d|RD_t|I3	}, /* dsubu 0*/
+{"drem",    "d,v,t",	3,    (int) M_DREM_3,	INSN_MACRO	},
+{"drem",    "d,v,I",	3,    (int) M_DREM_3I,	INSN_MACRO	},
+{"dremu",   "d,v,t",	3,    (int) M_DREMU_3,	INSN_MACRO	},
+{"dremu",   "d,v,I",	3,    (int) M_DREMU_3I,	INSN_MACRO	},
+{"dsllv",   "d,t,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s|I3},
+{"dsll",    "d,w,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s|I3}, /* dsllv */
+{"dsll",    "d,w,<",	0x00000038, 0xffe0003f,	WR_d|RD_t|I3	},
+{"dsll32",  "d,w,<",	0x0000003c, 0xffe0003f, WR_d|RD_t|I3	},
+{"dsrav",   "d,t,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s|I3},
+{"dsra",    "d,w,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s|I3}, /* dsrav */
+{"dsra",    "d,w,<",	0x0000003b, 0xffe0003f,	WR_d|RD_t|I3	},
+{"dsra32",  "d,w,<",	0x0000003f, 0xffe0003f, WR_d|RD_t|I3	},
+{"dsrlv",   "d,t,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s|I3},
+{"dsrl",    "d,w,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s|I3}, /* dsrlv */
+{"dsrl",    "d,w,<",	0x0000003a, 0xffe0003f,	WR_d|RD_t|I3	},
+{"dsrl32",  "d,w,<",	0x0000003e, 0xffe0003f, WR_d|RD_t|I3	},
+{"dsub",    "d,v,t",	0x0000002e, 0xfc0007ff,	WR_d|RD_s|RD_t|I3},
+{"dsub",    "d,v,I",	3,    (int) M_DSUB_I,	INSN_MACRO	},
+{"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t|I3},
+{"dsubu",   "d,v,I",	3,    (int) M_DSUBU_I,	INSN_MACRO	},
+{"eret",    "",		0x42000018, 0xffffffff, I3		},
+{"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|I3	},
+{"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|I3	},
+{"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|I2	},
+{"floor.w.s", "D,S",	0x4600000f, 0xffff003f, WR_D|RD_S|I2	},
 {"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s	},
 {"j",       "s",	0x00000008, 0xfc1fffff,	UBD|RD_s	},
 {"j",       "a",	0x08000000, 0xfc000000,	UBD		},
 {"jalr",    "s",	0x0000f809, 0xfc1fffff,	UBD|RD_s|WR_d	},
 {"jalr",    "d,s",	0x00000009, 0xfc1f07ff,	UBD|RD_s|WR_d	},
 {"jal",     "d,s",	0x00000009, 0xfc1f07ff,	UBD|RD_s|WR_d	},/* jalr */
-{"jal",     "s",	0x0000f809, 0xfc1fffff,	UBD|RD_s|WR_d	},/* jalr $ra */
+{"jal",     "s",	0x0000f809, 0xfc1fffff,	UBD|RD_s|WR_d	},/* jalr $ra*/
 {"jal",     "a",	0x0c000000, 0xfc000000,	UBD|WR_31	},
+{"l.d",     "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
 {"l.d",     "T,o(b)",	0,    (int) M_L_DOB,	INSN_MACRO	},
 {"l.d",     "T,A(b)",	0,    (int) M_L_DAB,	INSN_MACRO	},
 {"la",      "t,A",	0,    (int) M_LA,	INSN_MACRO	},
@@ -205,8 +309,21 @@ const struct mips_opcode mips_opcodes[] = {
 {"lb",      "t,A(b)",	0,    (int) M_LB_AB,	INSN_MACRO	},
 {"lbu",     "t,o(b)",	0x90000000, 0xfc000000,	LDD|RD_b|WR_t	},
 {"lbu",     "t,A(b)",	0,    (int) M_LBU_AB,	INSN_MACRO	},
+{"ld",	    "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b|I3	},
 {"ld",      "t,o(b)",	0,    (int) M_LD_OB,	INSN_MACRO	},
 {"ld",      "t,A(b)",	0,    (int) M_LD_AB,	INSN_MACRO	},
+{"ldc1",    "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
+{"ldc1",    "E,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
+{"ldc1",    "T,A(b)",	2,    (int) M_LDC1_AB,	INSN_MACRO	},
+{"ldc1",    "E,A(b)",	2,    (int) M_LDC1_AB,	INSN_MACRO	},
+{"ldc2",    "E,o(b)",	0xd8000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
+{"ldc2",    "E,A(b)",	2,    (int) M_LDC2_AB,	INSN_MACRO	},
+{"ldc3",    "E,o(b)",	0xdc000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
+{"ldc3",    "E,A(b)",	2,    (int) M_LDC3_AB,	INSN_MACRO	},
+{"ldl",	    "t,o(b)",	0x68000000, 0xfc000000, LDD|WR_t|RD_b|I3},
+{"ldl",	    "t,A(b)",	3,    (int) M_LDL_AB,	INSN_MACRO	},
+{"ldr",	    "t,o(b)",	0x6c000000, 0xfc000000, LDD|WR_t|RD_b|I3},
+{"ldr",     "t,A(b)",	3,    (int) M_LDR_AB,	INSN_MACRO	},
 {"lh",      "t,o(b)",	0x84000000, 0xfc000000,	LDD|RD_b|WR_t	},
 {"lh",      "t,A(b)",	0,    (int) M_LH_AB,	INSN_MACRO	},
 {"lhu",     "t,o(b)",	0x94000000, 0xfc000000,	LDD|RD_b|WR_t	},
@@ -216,38 +333,48 @@ const struct mips_opcode mips_opcodes[] = {
 {"li.d",    "T,L",	0,    (int) M_LI_DD,	INSN_MACRO	},
 {"li.s",    "t,f",	0,    (int) M_LI_S,	INSN_MACRO	},
 {"li.s",    "T,l",	0,    (int) M_LI_SS,	INSN_MACRO	},
+{"ll",	    "t,o(b)",	0xc0000000, 0xfc000000, LDD|RD_b|WR_t|I2},
+{"ll",	    "t,A(b)",	2,    (int) M_LL_AB,	INSN_MACRO	},
+{"lld",	    "t,o(b)",	0xd0000000, 0xfc000000, LDD|RD_b|WR_t|I3},
+{"lld",     "t,A(b)",	3,    (int) M_LLD_AB,	INSN_MACRO	},
 {"lui",     "t,u",	0x3c000000, 0xffe00000,	WR_t		},
 {"lw",      "t,o(b)",	0x8c000000, 0xfc000000,	LDD|RD_b|WR_t	},
 {"lw",      "t,A(b)",	0,    (int) M_LW_AB,	INSN_MACRO	},
-{"lwc0",    "E,o(b)",	0xc0000000, 0xfc000000,	COD|RD_b|WR_CC	},
+{"lwc0",    "E,o(b)",	0xc0000000, 0xfc000000,	CLD|RD_b|WR_CC	},
 {"lwc0",    "E,A(b)",	0,    (int) M_LWC0_AB,	INSN_MACRO	},
-{"lwc1",    "T,o(b)",	0xc4000000, 0xfc000000,	COD|RD_b|WR_T	},
-{"lwc1",    "E,o(b)",	0xc4000000, 0xfc000000,	COD|RD_b|WR_T	},
+{"lwc1",    "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T	},
+{"lwc1",    "E,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T	},
 {"lwc1",    "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO	},
 {"lwc1",    "E,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO	},
-{"l.s",     "T,o(b)",	0xc4000000, 0xfc000000,	COD|RD_b|WR_T	}, /* lwc1 */
+{"l.s",     "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T	}, /* lwc1 */
 {"l.s",     "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO	},
-{"lwc2",    "E,o(b)",	0xc8000000, 0xfc000000,	COD|RD_b|WR_CC	},
+{"lwc2",    "E,o(b)",	0xc8000000, 0xfc000000,	CLD|RD_b|WR_CC	},
 {"lwc2",    "E,A(b)",	0,    (int) M_LWC2_AB,	INSN_MACRO	},
-{"lwc3",    "E,o(b)",	0xcc000000, 0xfc000000,	COD|RD_b|WR_CC	},
+{"lwc3",    "E,o(b)",	0xcc000000, 0xfc000000,	CLD|RD_b|WR_CC	},
 {"lwc3",    "E,A(b)",	0,    (int) M_LWC3_AB,	INSN_MACRO	},
 {"lwl",     "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t	},
 {"lwl",     "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO	},
+{"lcache",  "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t|I2}, /* same */
+{"lcache",  "t,A(b)",	2,    (int) M_LWL_AB,	INSN_MACRO	}, /* as lwl */
 {"lwr",     "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t	},
 {"lwr",     "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO	},
-{"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LDD|WR_t|RD_C0	},
-{"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LDD|WR_t|RD_S	},
-{"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LDD|WR_t|RD_S	},
-{"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LDD|WR_t|RD_C2	},
-{"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LDD|WR_t|RD_C3	},
+{"flush",   "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t|I2}, /* same */
+{"flush",   "t,A(b)",	2,    (int) M_LWR_AB,	INSN_MACRO	}, /* as lwr */
+{"lwu",     "t,o(b)",	0xbc000000, 0xfc000000,	LDD|RD_b|WR_t|I3},
+{"lwu",     "t,A(b)",	3,    (int) M_LWU_AB,	INSN_MACRO	},
+{"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0	},
+{"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S	},
+{"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S	},
+{"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2	},
+{"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LCD|WR_t|RD_C3	},
 {"mfhi",    "d",	0x00000010, 0xffff07ff,	WR_d|RD_HI	},
 {"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO	},
 {"mov.d",   "D,S",	0x46200006, 0xffff003f,	WR_D|RD_S	},
 {"mov.s",   "D,S",	0x46000006, 0xffff003f,	WR_D|RD_S	},
 /* move is at the top of the table.  */
 {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC	},
-{"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_D	},
-{"mtc1",    "t,G",	0x44800000, 0xffe007ff,	COD|RD_t|WR_D	},
+{"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S	},
+{"mtc1",    "t,G",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S	},
 {"mtc2",    "t,G",	0x48800000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC	},
 {"mtc3",    "t,G",	0x4c800000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC	},
 {"mthi",    "s",	0x00000011, 0xfc1fffff,	RD_s|WR_HI	},
@@ -282,12 +409,34 @@ const struct mips_opcode mips_opcodes[] = {
 {"rol",     "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO	},
 {"ror",     "d,v,t",	0,    (int) M_ROR,	INSN_MACRO	},
 {"ror",     "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO	},
-{"s.d",     "T,o(b)",	0,    (int) M_S_DOB,	INSN_MACRO	},
-{"s.d",     "T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO	},
+{"round.l.d", "D,S",	0x46200008, 0xffff003f, WR_D|RD_S|I3	},
+{"round.l.s", "D,S",	0x46000008, 0xffff003f, WR_D|RD_S|I3	},
+{"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|I2	},
+{"round.w.s", "D,S",	0x4600000c, 0xffff003f, WR_D|RD_S|I2	},
 {"sb",      "t,o(b)",	0xa0000000, 0xfc000000,	RD_t|RD_b	},
 {"sb",      "t,A(b)",	0,    (int) M_SB_AB,	INSN_MACRO	},
+{"sc",	    "t,o(b)",	0xe0000000, 0xfc000000, RD_t|RD_b|I2	},
+{"sc",	    "t,A(b)",	2,    (int) M_SC_AB,	INSN_MACRO	},
+{"scd",	    "t,o(b)",	0xf0000000, 0xfc000000, RD_t|RD_b|I3	},
+{"scd",	    "t,A(b)",	3,    (int) M_SCD_AB,	INSN_MACRO	},
+{"sd",	    "t,o(b)",	0xfc000000, 0xfc000000,	RD_t|RD_b|I3	},
 {"sd",      "t,o(b)",	0,    (int) M_SD_OB,	INSN_MACRO	},
 {"sd",      "t,A(b)",	0,    (int) M_SD_AB,	INSN_MACRO	},
+{"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, RD_T|RD_b|I2	},
+{"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, RD_T|RD_b|I2	},
+{"sdc1",    "T,A(b)",	2,    (int) M_SDC1_AB,	INSN_MACRO	},
+{"sdc1",    "E,A(b)",	2,    (int) M_SDC1_AB,	INSN_MACRO	},
+{"sdc2",    "E,o(b)",	0xf8000000, 0xfc000000, RD_C2|RD_b|I2	},
+{"sdc2",    "E,A(b)",	2,    (int) M_SDC2_AB,	INSN_MACRO	},
+{"sdc3",    "E,o(b)",	0xfc000000, 0xfc000000, RD_C3|RD_b|I2	},
+{"sdc3",    "E,A(b)",	2,    (int) M_SDC3_AB,	INSN_MACRO	},
+{"s.d",     "T,o(b)",	0xf4000000, 0xfc000000, RD_T|RD_b|I2	},
+{"s.d",     "T,o(b)",	0,    (int) M_S_DOB,	INSN_MACRO	},
+{"s.d",     "T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO	},
+{"sdl",     "t,o(b)",	0xb0000000, 0xfc000000,	RD_t|RD_b|I3	},
+{"sdl",     "t,A(b)",	3,    (int) M_SDL_AB,	INSN_MACRO	},
+{"sdr",     "t,o(b)",	0xb4000000, 0xfc000000,	RD_t|RD_b|I3	},
+{"sdr",     "t,A(b)",	3,    (int) M_SDR_AB,	INSN_MACRO	},
 {"seq",     "d,v,t",	0,    (int) M_SEQ,	INSN_MACRO	},
 {"seq",     "d,v,I",	0,    (int) M_SEQ_I,	INSN_MACRO	},
 {"sge",     "d,v,t",	0,    (int) M_SGE,	INSN_MACRO	},
@@ -315,6 +464,8 @@ const struct mips_opcode mips_opcodes[] = {
 {"sltu",    "d,v,I",	0,    (int) M_SLTU_I,	INSN_MACRO	},
 {"sne",     "d,v,t",	0,    (int) M_SNE,	INSN_MACRO	},
 {"sne",     "d,v,I",	0,    (int) M_SNE_I,	INSN_MACRO	},
+{"sqrt.d",  "D,S",	0x46200004, 0xffff003f, WR_D|RD_S|I2	},
+{"sqrt.w",  "D,S",	0x46000004, 0xffff003f, WR_D|RD_S|I2	},
 {"srav",    "d,t,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s	},
 {"sra",     "d,w,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s	}, /* srav */
 {"sra",     "d,w,<",	0x00000003, 0xffe0003f,	WR_d|RD_t	},
@@ -343,15 +494,50 @@ const struct mips_opcode mips_opcodes[] = {
 {"swc3",    "E,A(b)",	0,    (int) M_SWC3_AB,	INSN_MACRO	},
 {"swl",     "t,o(b)",	0xa8000000, 0xfc000000,	RD_t|RD_b	},
 {"swl",     "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO	},
+{"scache",  "t,o(b)",	0xa8000000, 0xfc000000,	RD_t|RD_b|I2	}, /* same */
+{"scache",  "t,A(b)",	2,    (int) M_SWL_AB,	INSN_MACRO	}, /* as swl */
 {"swr",     "t,o(b)",	0xb8000000, 0xfc000000,	RD_t|RD_b	},
 {"swr",     "t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO	},
+{"invalidate", "t,o(b)",0xb8000000, 0xfc000000,	RD_t|RD_b|I2	}, /* same */
+{"invalidate", "t,A(b)",2,    (int) M_SWR_AB,	INSN_MACRO	}, /* as swr */
+{"sync",    "",		0x0000000f, 0xffffffff, I2		},
 {"syscall", "",		0x0000000c, 0xffffffff,	INSN_TRAP	},
 {"syscall", "B",	0x0000000c, 0xfc00003f,	INSN_TRAP	},
+{"teqi",    "s,j",	0x040c0000, 0xfc1f0000, RD_s|I2		},
+{"teq",	    "s,t",	0x00000034, 0xfc00003f, RD_s|RD_t|I2	},
+{"teq",     "s,j",	0x040c0000, 0xfc1f0000, RD_s|I2		}, /* teqi */
+{"teq",     "s,I",	2,    (int) M_TEQ_I,	INSN_MACRO	},
+{"tgei",    "s,j",	0x04080000, 0xfc1f0000, RD_s|I2		},
+{"tge",	    "s,t",	0x00000030, 0xfc00003f,	RD_s|RD_t|I2	},
+{"tge",     "s,j",	0x04080000, 0xfc1f0000, RD_s|I2		}, /* tgei */
+{"tge",	    "s,I",	2,    (int) M_TGE_I,    INSN_MACRO	},
+{"tgeiu",   "s,j",	0x04090000, 0xfc1f0000, RD_s|I2		},
+{"tgeu",    "s,t",	0x00000031, 0xfc00003f, RD_s|RD_t|I2	},
+{"tgeu",    "s,j",	0x04090000, 0xfc1f0000, RD_s|I2		}, /* tgeiu */
+{"tgeu",    "s,I",	2,    (int) M_TGEU_I,	INSN_MACRO	},
 {"tlbp",    "",		0x42000008, 0xffffffff,	INSN_TLB	},
 {"tlbr",    "",		0x42000001, 0xffffffff,	INSN_TLB	},
 {"tlbwi",   "",		0x42000002, 0xffffffff,	INSN_TLB	},
 {"tlbwr",   "",		0x42000006, 0xffffffff,	INSN_TLB	},
+{"tlti",    "s,j",	0x040a0000, 0xfc1f0000,	RD_s|I2		},
+{"tlt",     "s,t",	0x00000032, 0xfc00003f, RD_s|RD_t|I2	},
+{"tlt",     "s,j",	0x040a0000, 0xfc1f0000,	RD_s|I2		}, /* tlti */
+{"tlt",     "s,I",	2,    (int) M_TLT_I,	INSN_MACRO	},
+{"tltiu",   "s,j",	0x040b0000, 0xfc1f0000, RD_s|I2		},
+{"tltu",    "s,t",	0x00000033, 0xfc00003f, RD_s|RD_t|I2	},
+{"tltu",    "s,j",	0x040b0000, 0xfc1f0000, RD_s|I2		}, /* tltiu */
+{"tltu",    "s,I",	2,    (int) M_TLTU_I,	INSN_MACRO	},
+{"tnei",    "s,j",	0x040e0000, 0xfc1f0000, RD_s|I2		},
+{"tne",     "s,t",	0x00000036, 0xfc00003f, RD_s|RD_t|I2	},
+{"tne",     "s,j",	0x040e0000, 0xfc1f0000, RD_s|I2		}, /* tnei */
+{"tne",     "s,I",	2,    (int) M_TNE_I,	INSN_MACRO	},
+{"trunc.l.d", "D,S",	0x46200009, 0xffff003f, WR_D|RD_S|I3	},
+{"trunc.l.s", "D,S",	0x46000009, 0xffff003f,	WR_D|RD_S|I3	},
+{"trunc.w.d", "D,S",	0x4620000d, 0xffff003f, WR_D|RD_S|I2	},
+{"trunc.w.d", "D,S,x",	0x4620000d, 0xffff003f, WR_D|RD_S|I2	},
 {"trunc.w.d", "D,S,t",	0,    (int) M_TRUNCWD,	INSN_MACRO	},
+{"trunc.w.s", "D,S",	0x4600000d, 0xffff003f,	WR_D|RD_S|I2	},
+{"trunc.w.s", "D,S,x",	0x4600000d, 0xffff003f,	WR_D|RD_S|I2	},
 {"trunc.w.s", "D,S,t",	0,    (int) M_TRUNCWS,	INSN_MACRO	},
 {"ulh",     "t,o(b)",	0,    (int) M_ULH,	INSN_MACRO	},
 {"ulh",     "t,A",	0,    (int) M_ULH_A,	INSN_MACRO	},