MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support

Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:

1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
   MIPS16e2 instructions[1], for assembly and disassembly,

2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
   regular MIPS instructions[2], for assembly and disassembly,

3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
   extension.

4. Support for interAptiv MR2 architecture selection for assembly, in
   the form of the `-march=interaptiv-mr2' command-line option and its
   corresponding `arch=interaptiv-mr2' setting for the `.set' and
   `.module' pseudo-ops.

5. Support for interAptiv MR2 architecture selection for disassembly,
   in the form of the `mips:interaptiv-mr2' target architecture, for
   use e.g. with the `-m' command-line option for `objdump'.

Parts of this change by Matthew Fortune and Andrew Bennett.

References:

[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
    Imagination Technologies Ltd., Document Number: MD00904, Revision
    02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
    Instructions", pp. 878-883

[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917

	include/
	* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
	(AFL_EXT_INTERAPTIV_MR2): Likewise.
	* opcode/mips.h: Document new operand codes defined.
	(INSN_INTERAPTIV_MR2): New macro.
	(INSN_CHIP_MASK): Adjust accordingly.
	(CPU_INTERAPTIV_MR2): New macro.
	(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
	(MIPS16_ALL_ARGS): Rename to...
	(MIPS_SVRS_ALL_ARGS): ... this.
	(MIPS16_ALL_STATICS): Rename to...
	(MIPS_SVRS_ALL_STATICS): ... this.

	bfd/
	* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
	* cpu-mips.c (I_interaptiv_mr2): New enum value.
	(arch_info_struct): Add "mips:interaptiv-mr2" entry.
	* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
	case.
	(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
	(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
	(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
	(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
	`bfd_mach_mips_interaptiv_mr2' entries.
	* bfd-in2.h: Regenerate.

	opcodes/
	* mips-formats.h (INT_BIAS): New macro.
	(INT_ADJ): Redefine in INT_BIAS terms.
	* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
	(mips_print_save_restore): New function.
	(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
	(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
	call.
	(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
	(print_mips16_insn_arg): Call `mips_print_save_restore' for
	OP_SAVE_RESTORE_LIST handling, factored out from here.
	* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
	(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
	(mips_builtin_opcodes): Add "restore" and "save" entries.
	* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
	(IAMR2): New macro.
	(mips16_opcodes): Add "copyw" and "ucopyw" entries.

	binutils/
	* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
	(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
	* NEWS: Mention Imagination interAptiv MR2 processor support.

	gas/
	* config/tc-mips.c (validate_mips_insn): Handle
	OP_SAVE_RESTORE_LIST specially.
	(mips_encode_save_restore, mips16_encode_save_restore): New
	functions.
	(match_save_restore_list_operand): Factor out SAVE/RESTORE
	operand insertion into the instruction word or halfword to these
	new functions.
	(mips_cpu_info_table): Add "interaptiv-mr2" entry.

	* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
	`-march=' argument list.

1 files changed, 11 insertions, 0 deletions

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index e47d1fd..b151bae 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -46,6 +46,7 @@ decode_mips_operand (const char *p)
 	case 'a': INT_ADJ (19, 0, 262143, 2, FALSE);
 	case 'b': INT_ADJ (18, 0, 131071, 3, FALSE);
 	case 'd': SPECIAL (0, 0, REPEAT_DEST_REG);
+	case 'm': SPECIAL (20, 6, SAVE_RESTORE_LIST);
 	case 's': SPECIAL (5, 21, NON_ZERO_REG);
 	case 't': SPECIAL (5, 16, NON_ZERO_REG);
 	case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, FALSE);
@@ -232,6 +233,7 @@ decode_mips_operand (const char *p)
 #define RD_2	INSN_READ_2
 #define RD_3	INSN_READ_3
 #define RD_4	INSN_READ_4
+#define RD_31	INSN2_READ_GPR_31
 #define MOD_1	(WR_1|RD_1)
 #define MOD_2	(WR_2|RD_2)
 
@@ -261,6 +263,10 @@ decode_mips_operand (const char *p)
 #define RD_HILO RD_HI|RD_LO
 #define MOD_HILO WR_HILO|RD_HILO
 
+#define RD_SP	INSN2_READ_SP
+#define WR_SP	INSN2_WRITE_SP
+#define MOD_SP	(RD_SP|WR_SP)
+
 #define IS_M    INSN_MULT
 
 #define WR_MACC INSN2_WRITE_MDMX_ACC
@@ -321,6 +327,7 @@ decode_mips_operand (const char *p)
 #define IOCT2	(INSN_OCTEON2 | INSN_OCTEON3)
 #define IOCT3	INSN_OCTEON3
 #define XLR     INSN_XLR
+#define IAMR2	INSN_INTERAPTIV_MR2
 #define IVIRT	ASE_VIRT
 #define IVIRT64	ASE_VIRT64
 
@@ -3151,6 +3158,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cfcmsa",		"+k,+n",	0x787e0019, 0xffff003f,	WR_1|CM,		0,		0,		MSA,	0 },
 {"move.v",		"+d,+e",	0x78be0019, 0xffff003f,	WR_1|RD_2,		0,		0,		MSA,	0 },
 
+/* interAptiv MR2 instruction extensions.  */
+{"restore",		"-m",		0x7000001f, 0xfc00603f, WR_31|NODS,		MOD_SP,		IAMR2,		0,	0 },
+{"save",		"-m",		0x7000201f, 0xfc00603f, NODS,			RD_31|MOD_SP,	IAMR2,		0,	0 },
+
 /* User Defined Instruction.  */
 {"udi0",		"s,t,d,+1",	0x70000010, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi0",		"s,t,+2",	0x70000010, 0xfc00003f,	UDI,			0,		I33,		0,	0 },