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| author | Andrew Bennett <andrew.bennett@imgtec.com> | 2015-03-13 22:02:16 +0000 |
|---|---|---|
| committer | Andrew Bennett <andrew.bennett@imgtec.com> | 2015-03-13 22:02:16 +0000 |
| commit | 21e20815a20606a858f626e09944f29ee5ebee82 (patch) | |
| tree | 91c3c3d2c423031b06542ea897d2298240df6e94 /opcodes/mips-opc.c | |
| parent | 61a12cfa7b25746914493cc0d94e5053a8492aa5 (diff) | |
| download | gdb-21e20815a20606a858f626e09944f29ee5ebee82.zip gdb-21e20815a20606a858f626e09944f29ee5ebee82.tar.gz gdb-21e20815a20606a858f626e09944f29ee5ebee82.tar.bz2 | |
Add support for MIPS R6 evp and dvp instructions.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
gas/testsuite/
* gas/mips/r6.s: Add evp and dvp instructions.
* gas/mips/r6.d: Likewise.
* gas/mips/r6-n32.d: Likewise.
* gas/mips/r6-n64.d: Likewise.
Diffstat (limited to 'opcodes/mips-opc.c')
| -rw-r--r-- | opcodes/mips-opc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 0472b5b..f43f9f5 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1147,6 +1147,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, 0, MT32, 0 }, {"dvpe", "t", 0x41600001, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, +{"dvp", "", 0x41600024, 0xffffffff, TRAP, 0, I37, 0, 0 }, +{"dvp", "t", 0x41600024, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 }, {"ei", "", 0x42000038, 0xffffffff, WR_C0, 0, EE, 0, 0 }, {"ei", "", 0x41606020, 0xffffffff, WR_C0, 0, I33, 0, 0 }, {"ei", "t", 0x41606020, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 }, @@ -1156,6 +1158,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"eretnc", "", 0x42000058, 0xffffffff, NODS, 0, I36, 0, 0 }, {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 }, {"evpe", "t", 0x41600021, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, +{"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I37, 0, 0 }, +{"evp", "t", 0x41600004, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 }, {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 }, {"exts32", "t,r,+p,+s", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, {"exts", "t,r,+P,+S", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* exts32 */ |