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| author | Chris Demetriou <cgd@google.com> | 2002-12-31 08:11:18 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2002-12-31 08:11:18 +0000 |
| commit | bbcc08074ff8a8e6cb1acfe4f59bc827ada47fc6 (patch) | |
| tree | 093995456819b1ebd70957b755a49c060ddba725 /opcodes/mips-opc.c | |
| parent | b337e146e538a29772b785c8b96a14c654bc3247 (diff) | |
| download | gdb-bbcc08074ff8a8e6cb1acfe4f59bc827ada47fc6.zip gdb-bbcc08074ff8a8e6cb1acfe4f59bc827ada47fc6.tar.gz gdb-bbcc08074ff8a8e6cb1acfe4f59bc827ada47fc6.tar.bz2 | |
[ gas/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (validate_mips_insn, mips_ip): Recognize
the "+D" operand, which will be used only by the disassembler.
[ gas/testsuite/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0sel-names-mips32.d: New test.
* gas/mips/cp0sel-names-mips32r2.d: New test.
* gas/mips/cp0sel-names-mips64.d: New test.
* gas/mips/cp0sel-names-numeric.d: New test.
* gas/mips/cp0sel-names-sb1.d: New test.
* gas/mips/cp0sel-names.s: New test source file.
* gas/mips/mips.exp: Run new tests.
[ include/opcode/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* mips.h: Note that the "+D" operand type name is now used.
[ opcodes/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0sel_name): New structure.
(mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2)
(mips_cp0sel_names_sb1): New arrays.
(mips_arch_choice): New structure members "cp0sel_names" and
"cp0sel_names_len".
(mips_arch_choices): Add references to new cp0sel_names arrays
as appropriate, and make all existing entries reference
appropriate mips_XXX_names_numeric arrays rather than simply
using NULL.
(mips_cp0sel_names, mips_cp0sel_names_len): New variables.
(lookup_mips_cp0sel_name): New function.
(set_default_mips_dis_options): Set mips_cp0sel_names and
mips_cp0sel_names_len as appropriate. Remove now-unnecessary
checks for NULL register name arrays.
(parse_mips_dis_option): Likewise.
(print_insn_arg): Handle "+D" operand type.
* mips-opc.c (mips_builtin_opcodes): Add new "+D" variants
of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register
names symbolically.
Diffstat (limited to 'opcodes/mips-opc.c')
| -rw-r--r-- | opcodes/mips-opc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index c35aa06..436420e 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -521,8 +521,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, N411 }, {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 }, +{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 }, {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 }, {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 }, +{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 }, {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 }, {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, @@ -714,6 +716,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1|N5 }, {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1|N5 }, {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, +{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 }, {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 }, {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, @@ -777,6 +780,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, M1|N5 }, {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, M1|N5 }, {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 }, +{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 }, {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 }, {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, |