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| author | Chris Demetriou <cgd@google.com> | 2001-10-18 01:42:16 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2001-10-18 01:42:16 +0000 |
| commit | 2228315b47c1647bd28e7d7d0074fd23310080af (patch) | |
| tree | db91d877e14db26b9177119819df7e7ccda29838 /opcodes/mips-opc.c | |
| parent | c080b94227d8bb7d994b1ff41d7548019e6a9dc1 (diff) | |
| download | gdb-2228315b47c1647bd28e7d7d0074fd23310080af.zip gdb-2228315b47c1647bd28e7d7d0074fd23310080af.tar.gz gdb-2228315b47c1647bd28e7d7d0074fd23310080af.tar.bz2 | |
[gas/testsuite/ChangeLog]
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* gas/mips/mips.exp (sb1-ext-ps): New test to test
SB-1 core's paired-single extensions to the MIPS64 ISA.
* gas/mips/sb1-ext-ps.d: New file.
* gas/mips/sb1-ext-ps.s: New file.
[include/opcode/ChangeLog]
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips.h (INSN_SB1): New cpu-specific instruction bit.
(OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
if cpu is CPU_SB1.
[opcodes/ChangeLog]
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_isa_type): Make the ISA used to disassemble
SB-1 binaries include instructions specific to the SB-1.
* mips-opc.c (SB1): New definition.
(mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps",
"recip.ps", "rsqrt.ps", and "sqrt.ps".
Diffstat (limited to 'opcodes/mips-opc.c')
| -rw-r--r-- | opcodes/mips-opc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 5c2c792..578f22c 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -87,6 +87,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define V1 INSN_4100 #define T3 INSN_3900 #define M1 INSN_10000 +#define SB1 INSN_SB1 #define G1 (T3 \ ) @@ -384,6 +385,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 }, {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, +{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, SB1 }, /* For divu, see the comments about div. */ {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 }, @@ -652,6 +654,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 }, {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 }, +{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 }, {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 }, @@ -669,6 +672,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 }, {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 }, {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 }, +{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 }, {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 }, {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 }, @@ -730,6 +734,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 }, {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 }, {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */ {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 }, |