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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 09:32:55 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 09:32:55 +0000 |
| commit | fa7616a4c7661cf786f3eaa9282072ca5dd8099c (patch) | |
| tree | 11ef2eb4ec10903834cb68365334d7a26b77c1b0 /opcodes/mips-opc.c | |
| parent | 7c0de7419bd4f1b4aa0bdb3c15b03615dbe3959a (diff) | |
| download | gdb-fa7616a4c7661cf786f3eaa9282072ca5dd8099c.zip gdb-fa7616a4c7661cf786f3eaa9282072ca5dd8099c.tar.gz gdb-fa7616a4c7661cf786f3eaa9282072ca5dd8099c.tar.bz2 | |
include/opcode/
* mips.h: Remove documentation of "+D" and "+T".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
and "+T" handling. Check for a "0" suffix when deciding whether to
use coprocessor 0 names. In that case, also check for ",H" selectors.
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
(mips_ip): Remove "+D" and "+T" handling.
gas/testsuite/
* gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names
for LWC0 and SWC0.
Diffstat (limited to 'opcodes/mips-opc.c')
| -rw-r--r-- | opcodes/mips-opc.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index d12701b..72f5842 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -724,18 +724,14 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3, 0, EE }, -{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, LCD|WR_t|RD_C0, 0, 0, IVIRT64 }, -{"dmfgc0", "t,+D", 0x40600100, 0xffe007f8, LCD|WR_t|RD_C0, 0, 0, IVIRT64 }, {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, LCD|WR_t|RD_C0, 0, 0, IVIRT64 }, {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32 }, {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, 0, MT32 }, {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3, 0, EE }, -{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, {"dmtgc0", "t,G", 0x40600300, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT64 }, -{"dmtgc0", "t,+D", 0x40600300, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT64 }, {"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT64 }, {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3, 0, SF }, {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3, 0, SF }, @@ -1010,7 +1006,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, 0, MT32 }, {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, 0, MT32 }, {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, 0, MT32 }, -{"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, 0, MT32 }, {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, 0, MT32 }, {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, 0, MT32 }, {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, 0, MT32 }, @@ -1026,10 +1021,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, 0, MT32 }, {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, 0, MT32 }, {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, -{"mfc0", "t,+D",0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, {"mfgc0", "t,G", 0x40600000, 0xffe007ff, LCD|WR_t|RD_C0, 0, 0, IVIRT }, -{"mfgc0", "t,+D", 0x40600000, 0xffe007f8, LCD|WR_t|RD_C0, 0, 0, IVIRT }, {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, LCD|WR_t|RD_C0, 0, 0, IVIRT }, {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, @@ -1123,10 +1116,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5|EE }, {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5|EE }, {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, -{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, {"mtgc0", "t,G", 0x40600200, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT }, -{"mtgc0", "t,+D", 0x40600200, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT }, {"mtgc0", "t,G,H", 0x40600200, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT }, {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, @@ -1154,7 +1145,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_s, 0, EE }, {"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_s, 0, EE }, {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, 0, MT32 }, -{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, 0, MT32 }, {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, 0, MT32 }, {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, 0, MT32 }, {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, 0, MT32 }, |