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| author | Henry Wong <henry@stuffedcow.net> | 2018-02-12 14:50:42 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@mips.com> | 2018-02-12 14:50:42 +0000 |
| commit | d2159fdc0f0ac1d0aaafab725b930e78a8793494 (patch) | |
| tree | 8003b1ce5358bf26c01eba1de7ee8215f5cc2bee /opcodes/mips-opc.c | |
| parent | 830db0485e19000985ccfdbacda4d4d5d62583bb (diff) | |
| download | gdb-d2159fdc0f0ac1d0aaafab725b930e78a8793494.zip gdb-d2159fdc0f0ac1d0aaafab725b930e78a8793494.tar.gz gdb-d2159fdc0f0ac1d0aaafab725b930e78a8793494.tar.bz2 | |
MIPS: Fix encoding for MIPSr6 sigrie instruction.
The instruction encoding for the MIPS r6 sigrie instruction seems to be
incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp,
and dvp), but should be 0x0417xxxx. See ISA reference[1][2].
References:
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies, Inc., Document
Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32
REGIMM Encoding of rt Field", p. 452
[2] "MIPS Architecture For Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Imagination Technologies, Inc.,
Document Number: MD00087, Revision 6.06, December 15, 2016, Table
A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581
opcodes/
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
gas/
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
Diffstat (limited to 'opcodes/mips-opc.c')
| -rw-r--r-- | opcodes/mips-opc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 180d613..b0c6195 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1867,7 +1867,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"sigrie", "u", 0x41700000, 0xffff0000, TRAP, 0, I37, 0, 0 }, +{"sigrie", "u", 0x04170000, 0xffff0000, TRAP, 0, I37, 0, 0 }, {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 }, {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 }, {"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, |