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| author | Andrew Bennett <andrew.bennett@imgtec.com> | 2019-04-22 15:12:09 -0700 |
|---|---|---|
| committer | Faraz Shahbazker <fshahbazker@wavecomp.com> | 2019-04-26 18:28:05 -0700 |
| commit | a45328b93bdd5399da8a9e56817e445cc2068edd (patch) | |
| tree | d611c35292391d313d6d99f80aa1495fdbdef046 /opcodes/mips-opc.c | |
| parent | 45f0ab12d463cb3999a4286e679bdef05884b3a3 (diff) | |
| download | gdb-a45328b93bdd5399da8a9e56817e445cc2068edd.zip gdb-a45328b93bdd5399da8a9e56817e445cc2068edd.tar.gz gdb-a45328b93bdd5399da8a9e56817e445cc2068edd.tar.bz2 | |
[MIPS] Add load-link, store-conditional paired instructions
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions
that were omitted from the initial spec. These instructions
are optional in implementations but not associated with any
ASE or pseudo-ASE. Their presence is indicated by the XNP bit
in the Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 228-229, pp. 354-357.
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 289-290 and pp. 458-460.
gas/
* config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
M_SCDP_AB>: New cases and expansions for paired instructions.
* testsuite/gas/mips/llpscp-32.s: New test source.
* testsuite/gas/mips/llpscp-64.s: Likewise.
* testsuite/gas/mips/llpscp-32.d: New test.
* testsuite/gas/mips/llpscp-64.d: Likewise.
* testsuite/gas/mips/mips.exp: Run the new tests.
* testsuite/gas/mips/r6.s: Add new instructions to test source.
* testsuite/gas/mips/r6-64.s: Likewise.
* testsuite/gas/mips/r6-64-n32.d: Check new instructions.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likwwise.
* testsuite/gas/mips/r6.d: Likewise.
include/
* opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
(M_SCWP_AB, M_SCDP_AB): Likewise.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
Diffstat (limited to 'opcodes/mips-opc.c')
| -rw-r--r-- | opcodes/mips-opc.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 91f6027..8db2952 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1300,6 +1300,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"lld", "t,+j(b)", 0x7c000037, 0xfc00007f, WR_1|RD_3|LM, 0, I69, 0, 0 }, {"lld", "t,o(b)", 0xd0000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, EE|I69 }, {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, EE }, +{"lldp", "t,d,s", 0x7c000077, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I69, 0, 0 }, +{"lldp", "t,d,A(b)", 0, (int) M_LLDP_AB, INSN_MACRO, 0, I69, 0, 0 }, +{"llwp", "t,d,s", 0x7c000076, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I37, 0, 0 }, +{"llwp", "t,d,A(b)", 0, (int) M_LLWP_AB, INSN_MACRO, 0, I37, 0, 0 }, {"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_1|RD_3|LM, 0, MMI, 0, 0 }, {"lq", "t,A(b)", 0, (int) M_LQ_AB, INSN_MACRO, 0, MMI, 0, 0 }, {"lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2|LM, 0, EE, 0, 0 }, @@ -1831,6 +1835,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"scd", "t,+j(b)", 0x7c000027, 0xfc00007f, MOD_1|RD_3|SM, 0, I69, 0, 0 }, {"scd", "t,o(b)", 0xf0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I3, 0, EE|I69 }, {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, EE }, +{"scdp", "t,d,s", 0x7c000067, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, I69, 0, 0 }, +{"scdp", "t,d,A(b)", 0, (int) M_SCDP_AB, INSN_MACRO, 0, I69, 0, 0 }, +{"scwp", "t,d,s", 0x7c000066, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, I37, 0, 0 }, +{"scwp", "t,d,A(b)", 0, (int) M_SCWP_AB, INSN_MACRO, 0, I37, 0, 0 }, /* The macro has to be first to handle o32 correctly. */ {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1, 0, 0 }, {"sd", "t,o(b)", 0xfc000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 }, |