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| author | Faraz Shahbazker <fshahbazker@wavecomp.com> | 2019-05-06 09:29:20 -0700 |
|---|---|---|
| committer | Faraz Shahbazker <fshahbazker@wavecomp.com> | 2019-05-10 21:36:32 -0700 |
| commit | 387e762476ff224ee40760910e73a3905a2c380a (patch) | |
| tree | 8cbc344599f40ab24af2cc94dbc05858f51949f2 /opcodes/mips-opc.c | |
| parent | 0067be51e9436c5bbd961a4f54c10dbd50c491ea (diff) | |
| download | gdb-387e762476ff224ee40760910e73a3905a2c380a.zip gdb-387e762476ff224ee40760910e73a3905a2c380a.tar.gz gdb-387e762476ff224ee40760910e73a3905a2c380a.tar.bz2 | |
Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6
Release 6 of the MIPS architecture does not have an ADDI instruction.
ADD/SUB instructions with immediate operands can be expanded to load
and immediate value and then perform the operation.
gas/
* config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>:
Add expansions for MIPS r6.
* testsuite/gas/mips/add.s: Enable tests for R6.
* testsuite/gas/mips/daddi.s: Annotate to test DADD for R6.
* testsuite/gas/mips/mipsr6@add.d: Likewise.
* gas/testsuite/gas/mips/mipsr6@dadd.d: New test.
* gas/testsuite/gas/mips/mips.exp: Run the new test.
opcodes/
* mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
macros for R6.
Diffstat (limited to 'opcodes/mips-opc.c')
| -rw-r--r-- | opcodes/mips-opc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 64b13c8..69b16be 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -666,7 +666,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, {"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 }, {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, I37 }, +{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 }, {"add", "D,S,T", 0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, {"add", "D,S,T", 0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, @@ -1015,7 +1015,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, 0, M3D, 0 }, {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 }, {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, I69 }, +{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 }, {"dadd", "D,S,T", 0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, I69 }, @@ -1173,7 +1173,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, I69 }, +{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, 0 }, {"dsub", "D,S,T", 0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, @@ -1955,7 +1955,7 @@ const struct mips_opcode mips_builtin_opcodes[] = /* ssnop is at the start of the table. */ {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1, 0, 0 }, {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, I37 }, +{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, 0 }, {"sub", "D,S,T", 0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, {"sub", "D,S,T", 0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, |