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author | Catherine Moore <clm@codesourcery.com> | 2013-11-19 05:25:32 -0800 |
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committer | Catherine Moore <clm@codesourcery.com> | 2013-11-19 05:25:32 -0800 |
commit | 8f8c3854e0ea5c632e12d3d9193f0eb6a690c2a0 (patch) | |
tree | a4603405088bb0f5cafcdc2ee64ba6eaa5ade98c /opcodes/mips-opc.c | |
parent | a8d14a88922c353d99250521a4fd2129a49b7810 (diff) | |
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2013-11-19 Catherine Moore <clm@codesourcery.com>
* micromips-opc.c (LM): Define.
(micromips_opcodes): Add LM to load instructions.
* mips-opc.c (prefe): Add LM attribute.
Diffstat (limited to 'opcodes/mips-opc.c')
-rw-r--r-- | opcodes/mips-opc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 9fb2d95..cd43185 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -2568,7 +2568,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_3, 0, 0, EVA, 0 }, {"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 }, -{"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_3, 0, 0, EVA, 0 }, +{"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_3|LM, 0, 0, EVA, 0 }, {"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 }, /* MSA Extension. */ {"sll.b", "+d,+e,+h", 0x7800000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, |