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| author | Faraz Shahbazker <Faraz.Shahbazker@mips.com> | 2018-06-14 21:34:49 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@mips.com> | 2018-06-14 21:34:49 +0100 |
| commit | 6f20c942c3dbc08d02f74e4d508e19f8617bc5e3 (patch) | |
| tree | 8657870580c22165d940be0b82c63920e75835ea /opcodes/mips-opc.c | |
| parent | 8993072900ae3980957f704a1e3e033a22a4dcac (diff) | |
| download | gdb-6f20c942c3dbc08d02f74e4d508e19f8617bc5e3.zip gdb-6f20c942c3dbc08d02f74e4d508e19f8617bc5e3.tar.gz gdb-6f20c942c3dbc08d02f74e4d508e19f8617bc5e3.tar.bz2 | |
MIPS: Add Global INValidate ASE support
Add support for the Global INValidate Application Specific Extension
for Release 6 of the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 187-191
bfd/
* elfxx-mips.c (print_mips_ases): Add GINV extension.
binutils/
* readelf.c (print_mips_ases): Add GINV extension.
gas/
* NEWS: Mention MIPS Global INValidate ASE support.
* config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV.
(md_longopts): Likewise.
(mips_ases): Define availability for GINV.
(mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV.
(md_show_usage): Add help for -mginv and -mno-ginv.
* doc/as.texinfo: Document -mginv, -mno-ginv.
* doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and
.set noginv.
* testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV
ASE.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Likewise.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ginv.d: New test.
* testsuite/gas/mips/ginv-err.d: New test.
* testsuite/gas/mips/ginv-err.l: New test stderr output.
* testsuite/gas/mips/ginv.s: New test source.
* testsuite/gas/mips/ginv-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
* elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
(AFL_ASE_MASK): Update to include AFL_ASE_GINV.
* opcode/mips.h: Document "+\" operand format.
(ASE_GINV): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
mips64r6 descriptors.
(parse_mips_ase_option): Handle -Mginv option.
(print_mips_disassembler_options): Document -Mginv.
* mips-opc.c (decode_mips_operand) <+\>: New operand format.
(GINV): New macro.
(mips_opcodes): Define ginvi and ginvt.
Diffstat (limited to 'opcodes/mips-opc.c')
| -rw-r--r-- | opcodes/mips-opc.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index d172801..1cbcbc6 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -139,6 +139,7 @@ decode_mips_operand (const char *p) case '\'': BRANCH (26, 0, 2); case '"': BRANCH (21, 0, 2); case ';': SPECIAL (10, 16, SAME_RS_RT); + case '\\': BIT (2, 8, 0); /* (0 .. 3) */ } break; @@ -408,6 +409,9 @@ decode_mips_operand (const char *p) #define CRC ASE_CRC #define CRC64 ASE_CRC64 +/* Global INValidate (GINV) support. */ +#define GINV ASE_GINV + /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either for arguments must apear in the correct order in this table for the @@ -3361,6 +3365,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"crc32cw", "t,s,-d", 0x7c00018f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, {"crc32cd", "t,s,-d", 0x7c0001cf, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC64, 0 }, +/* MIPS Global INValidate (GINV) ASE. */ +{"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 }, +{"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 }, + /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the user to put in nops as necessary. These are at the end so that the |