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| author | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-15 13:04:19 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-15 13:57:07 +0100 |
| commit | fdfb475260daf591d05407ea7affa39122a5b7f6 (patch) | |
| tree | 0cdec9155f283ae80acad48f2b5d1c0feebadb65 /opcodes/mips-dis.c | |
| parent | a54d5f8bb3eb4772a94779a5d37b644aeee72bca (diff) | |
| download | gdb-fdfb475260daf591d05407ea7affa39122a5b7f6.zip gdb-fdfb475260daf591d05407ea7affa39122a5b7f6.tar.gz gdb-fdfb475260daf591d05407ea7affa39122a5b7f6.tar.bz2 | |
MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decoding
The `sel' operand of CP0 move instructions is a part of the base ISA and
has nothing to do with the MT ASE.
opcodes/
* mips-dis.c (print_insn_args) <default>: Remove an MT ASE
reference in CP0 move operand decoding.
Diffstat (limited to 'opcodes/mips-dis.c')
| -rw-r--r-- | opcodes/mips-dis.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 289f501..ab92add 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -1641,7 +1641,7 @@ print_insn_args (struct disassemble_info *info, && s[2] == 'H' && opcode->name[strlen (opcode->name) - 1] == '0') { - /* Coprocessor register 0 with sel field (MT ASE). */ + /* Coprocessor register 0 with sel field. */ const struct mips_cp0sel_name *n; unsigned int reg, sel; |