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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 09:41:04 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 09:41:04 +0000 |
| commit | e76ff5abe375e1e7535f7827db01bce70bc9710d (patch) | |
| tree | 258d8a6afed199e45671cb834a96d2c28f66af79 /opcodes/micromips-opc.c | |
| parent | fa7616a4c7661cf786f3eaa9282072ca5dd8099c (diff) | |
| download | gdb-e76ff5abe375e1e7535f7827db01bce70bc9710d.zip gdb-e76ff5abe375e1e7535f7827db01bce70bc9710d.tar.gz gdb-e76ff5abe375e1e7535f7827db01bce70bc9710d.tar.bz2 | |
include/opcode/
* mips.h: Remove "mi" documentation. Update "mh" documentation.
(OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
Delete.
(INSN2_WRITE_GPR_MHI): Rename to...
(INSN2_WRITE_GPR_MH): ...this.
opcodes/
* micromips-opc.c (WR_mhi): Rename to..
(WR_mh): ...this.
(micromips_opcodes): Update "movep" entry accordingly. Replace
"mh,mi" with "mh".
* mips-dis.c (micromips_to_32_reg_h_map): Rename to...
(micromips_to_32_reg_h_map1): ...this.
(micromips_to_32_reg_i_map): Rename to...
(micromips_to_32_reg_h_map2): ...this.
(print_micromips_insn): Remove "mi" case. Print both registers
in the pair for "mh".
gas/
* config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete.
(micromips_to_32_reg_h_map): Rename to...
(micromips_to_32_reg_h_map1): ...this.
(micromips_to_32_reg_i_map): Rename to...
(micromips_to_32_reg_h_map2): ...this.
(mips_lookup_reg_pair): New function.
(gpr_write_mask, macro): Adjust after above renaming.
(validate_micromips_insn): Remove "mi" handling.
(mips_ip): Likewise. Parse both registers in a pair for "mh".
Diffstat (limited to 'opcodes/micromips-opc.c')
| -rw-r--r-- | opcodes/micromips-opc.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index 64caf8a..9a9a32c 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -42,7 +42,7 @@ #define RD_mf INSN2_MOD_GPR_MF #define WR_mf INSN2_MOD_GPR_MF #define RD_mg INSN2_READ_GPR_MG -#define WR_mhi INSN2_WRITE_GPR_MHI +#define WR_mh INSN2_WRITE_GPR_MH #define RD_mj INSN2_READ_GPR_MJ #define WR_mj INSN2_WRITE_GPR_MJ #define RD_ml RD_mc /* Reuse, since the bit position is the same. */ @@ -703,10 +703,10 @@ const struct mips_opcode micromips_opcodes[] = {"mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 }, {"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 }, {"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 }, -{"movep", "mh,mi,mm,mn", 0x8400, 0xfc01, NODS, WR_mhi|RD_mmn, I1 }, +{"movep", "mh,mm,mn", 0x8400, 0xfc01, NODS, WR_mh|RD_mmn, I1 }, /* This macro is after the real instruction so that it only matches with -minsn32. */ -{"movep", "mh,mi,mm,mn", 0, (int) M_MOVEP, INSN_MACRO, 0, I1 }, +{"movep", "mh,mm,mn", 0, (int) M_MOVEP, INSN_MACRO, 0, I1 }, {"movf", "t,s,M", 0x5400017b, 0xfc001fff, WR_t|RD_s|RD_CC|FP_S|FP_D, 0, I1 }, {"movf.d", "T,S,M", 0x54000220, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 }, {"movf.s", "T,S,M", 0x54000020, 0xfc001fff, WR_T|RD_S|RD_CC|FP_S, 0, I1 }, |