diff options
| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-08-19 19:54:41 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-08-19 19:54:41 +0000 |
| commit | 5e0dc5bae9dbbbcbd4156cafc941d3f984bfc792 (patch) | |
| tree | 02a4eb07383caa751dea04d230cd6c456d3550c8 /opcodes/micromips-opc.c | |
| parent | 60f20e8ba8a846a278c11cedc1329486721ff01b (diff) | |
| download | gdb-5e0dc5bae9dbbbcbd4156cafc941d3f984bfc792.zip gdb-5e0dc5bae9dbbbcbd4156cafc941d3f984bfc792.tar.gz gdb-5e0dc5bae9dbbbcbd4156cafc941d3f984bfc792.tar.bz2 | |
include/opcode/
* mips.h (M_DEXT, M_DINS): Delete.
opcodes/
* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
Use +H rather than +C for the real "dext".
* mips-opc.c (mips_builtin_opcodes): Likewise.
gas/
* config/tc-mips.c (report_bad_range, report_bad_field): Delete.
(macro): Remove M_DEXT and M_DINS handling.
gas/testsuite/
* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
error messages to have the same form as the EXT and INS ones.
* gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d,
gas/mips/micromips-trap.d, gas/mips/micromips.d,
gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect
"dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
Diffstat (limited to 'opcodes/micromips-opc.c')
| -rw-r--r-- | opcodes/micromips-opc.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index 33dd57e..da1f708 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -544,8 +544,9 @@ const struct mips_opcode micromips_opcodes[] = {"dclo", "t,s", 0x58004b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, {"dclz", "t,s", 0x58005b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, {"deret", "", 0x0000e37c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I3, 0, 0 }, -{"dext", "t,r,+A,+C", 0x5800002c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{"dext", "t,r,+A,+H", 0x5800002c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{"dext", "t,r,+A,+G", 0x58000024, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dextm */ +{"dext", "t,r,+E,+H", 0x58000014, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dextu */ {"dextm", "t,r,+A,+G", 0x58000024, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, {"dextu", "t,r,+E,+H", 0x58000014, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* For ddiv, see the comments about div. */ @@ -560,8 +561,9 @@ const struct mips_opcode micromips_opcodes[] = {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, 0 }, {"di", "", 0x0000477c, 0xffffffff, RD_C0, 0, I1, 0, 0 }, {"di", "s", 0x0000477c, 0xffe0ffff, WR_1|RD_C0, 0, I1, 0, 0 }, -{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I3, 0, 0 }, {"dins", "t,r,+A,+B", 0x5800000c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{"dins", "t,r,+A,+F", 0x58000004, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dinsm */ +{"dins", "t,r,+E,+F", 0x58000034, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dinsu */ {"dinsm", "t,r,+A,+F", 0x58000004, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, {"dinsu", "t,r,+E,+F", 0x58000034, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* The MIPS assembler treats the div opcode with two operands as |