include/opcode/

	* mips.h: Document microMIPS DSP ASE usage.
	(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
	microMIPS DSP ASE support.
	(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
	(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
	(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
	(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
	(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
	(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
	(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.

	gas/
	* config/tc-mips.c (macro_build) <'2'>: Handle microMIPS.
	(macro) <M_BALIGN>: Update error handling.
	(validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases.
	<'7', '8', '0', '@', '^'>: Likewise.
	(mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS.
	<'9'>: Fix formatting.
	<'0', '@'>: Handle microMIPS.
	<'^'>: New case.

	gas/testsuite/
	* gas/mips/micromips@mips32-dsp.d: New.
	* gas/mips/micromips@mips32-dspr2.d: New.
	* gas/mips/mips32-dsp.d: Remove -mips32r2.
	* gas/mips/mips32-dspr2.d: Likewise.
	* gas/mips/mips.exp: (mips_create_arch): Use -mips64r2
	for micromips.  Use run_dump_test_arches to run dsp tests.

	opcodes/
	* micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
	(DSP_VOLA): Likewise.
	(D32, D33): Likewise.
	(micromips_opcodes): Add DSP ASE instructions.
	* micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
	<'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.

1 files changed, 172 insertions, 0 deletions

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 0f18c71..a15982d 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -99,6 +99,14 @@
 #define I1	INSN_ISA1
 #define I3	INSN_ISA3
 
+/* MIPS DSP ASE support.  */
+#define WR_a	WR_HILO		/* Write DSP accumulators (reuse WR_HILO).  */
+#define RD_a	RD_HILO		/* Read DSP accumulators (reuse RD_HILO).  */
+#define MOD_a	WR_a|RD_a
+#define DSP_VOLA INSN_NO_DELAY_SLOT
+#define D32	INSN_DSP
+#define D33	INSN_DSPR2
+
 /* MIPS MCU (MicroController) ASE support.  */
 #define MC	INSN_MCU
 
@@ -650,10 +658,12 @@ const struct mips_opcode micromips_opcodes[] =
 {"flush",   "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,		I1	},
 {"lwxs",    "d,t(b)",	0x00000118, 0xfc0007ff,	RD_b|RD_t|WR_d,		0,		I1	},
 {"madd",    "s,t",	0x0000cb3c, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	0,		I1	},
+{"madd",    "7,s,t",	0x00000abc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D32	},
 {"madd.d",  "D,R,S,T",	0x54000009, 0xfc00003f,	RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I1	},
 {"madd.s",  "D,R,S,T",	0x54000001, 0xfc00003f,	RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I1	},
 {"madd.ps", "D,R,S,T",	0x54000011, 0xfc00003f,	RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I1	},
 {"maddu",   "s,t",	0x0000db3c, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	0,		I1	},
+{"maddu",   "7,s,t",	0x00001abc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D32	},
 {"mfc0",    "t,G",	0x000000fc, 0xfc00ffff,	WR_t|RD_C0,		0,		I1	},
 {"mfc0",    "t,+D",	0x000000fc, 0xfc00c7ff,	WR_t|RD_C0,		0,		I1	},
 {"mfc0",    "t,G,H",	0x000000fc, 0xfc00c7ff,	WR_t|RD_C0,		0,		I1	},
@@ -665,8 +675,10 @@ const struct mips_opcode micromips_opcodes[] =
 {"mfhc2",   "t,G",	0x00008d3c, 0xfc00ffff,	WR_t|RD_C2,		0,		I1	},
 {"mfhi",    "mj",	    0x4600,     0xffe0,	RD_HI,			WR_mj,		I1	},
 {"mfhi",    "s",	0x00000d7c, 0xffe0ffff,	WR_s|RD_HI,		0,		I1	},
+{"mfhi",    "s,7",	0x0000007c, 0xffe03fff,	WR_s|RD_HI,		0,		D32	},
 {"mflo",    "mj",	    0x4640,     0xffe0,	RD_LO,			WR_mj,		I1	},
 {"mflo",    "s",	0x00001d7c, 0xffe0ffff,	WR_s|RD_LO,		0,		I1	},
+{"mflo",    "s,7",	0x0000107c, 0xffe03fff,	WR_s|RD_LO,		0,		D32	},
 {"mov.d",   "T,S",	0x5400207b, 0xfc00ffff,	WR_T|RD_S|FP_D,		0,		I1	},
 {"mov.s",   "T,S",	0x5400007b, 0xfc00ffff,	WR_T|RD_S|FP_S,		0,		I1	},
 {"mov.ps",  "T,S",	0x5400407b, 0xfc00ffff,	WR_T|RD_S|FP_D,		0,		I1	},
@@ -688,10 +700,12 @@ const struct mips_opcode micromips_opcodes[] =
 {"movz.s",  "D,S,t",	0x54000078, 0xfc0007ff,	WR_D|RD_S|RD_t|FP_S,	0,		I1	},
 {"movz.ps", "D,S,t",	0x54000278, 0xfc0007ff,	WR_D|RD_S|RD_t|FP_D,	0,		I1	},
 {"msub",    "s,t",	0x0000eb3c, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	0,		I1	},
+{"msub",    "7,s,t",	0x00002abc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D32	},
 {"msub.d",  "D,R,S,T",	0x54000029, 0xfc00003f,	RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I1	},
 {"msub.s",  "D,R,S,T",	0x54000021, 0xfc00003f,	RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I1	},
 {"msub.ps", "D,R,S,T",	0x54000031, 0xfc00003f,	RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I1	},
 {"msubu",   "s,t",	0x0000fb3c, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	0,		I1	},
+{"msubu",   "7,s,t",	0x00003abc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D32	},
 {"mtc0",    "t,G",	0x000002fc, 0xfc00ffff,	RD_t|WR_C0|WR_CC,	0,		I1	},
 {"mtc0",    "t,+D",	0x000002fc, 0xfc00c7ff,	RD_t|WR_C0|WR_CC,	0,		I1	},
 {"mtc0",    "t,G,H",	0x000002fc, 0xfc00c7ff,	RD_t|WR_C0|WR_CC,	0,		I1	},
@@ -702,7 +716,9 @@ const struct mips_opcode micromips_opcodes[] =
 {"mthc1",   "t,G",	0x5400383b, 0xfc00ffff,	RD_t|WR_S|FP_D,		0,		I1	},
 {"mthc2",   "t,G",	0x00009d3c, 0xfc00ffff,	RD_t|WR_C2|WR_CC,	0,		I1	},
 {"mthi",    "s",	0x00002d7c, 0xffe0ffff,	RD_s|WR_HI,		0,		I1	},
+{"mthi",    "s,7",	0x0000207c, 0xffe03fff,	RD_s|WR_HI,		0,		D32	},
 {"mtlo",    "s",	0x00003d7c, 0xffe0ffff,	RD_s|WR_LO,		0,		I1	},
+{"mtlo",    "s,7",	0x0000307c, 0xffe03fff,	RD_s|WR_LO,		0,		D32	},
 {"mul",     "d,v,t",	0x00000210, 0xfc0007ff,	WR_d|RD_s|RD_t|WR_HILO,	0,		I1	},
 {"mul",     "d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,		0,		I1	},
 {"mul.d",   "D,V,T",	0x540001b0, 0xfc0007ff,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
@@ -713,7 +729,9 @@ const struct mips_opcode micromips_opcodes[] =
 {"mulou",   "d,v,t",	0,    (int) M_MULOU,	INSN_MACRO,		0,		I1	},
 {"mulou",   "d,v,I",	0,    (int) M_MULOU_I,	INSN_MACRO,		0,		I1	},
 {"mult",    "s,t",	0x00008b3c, 0xfc00ffff,	RD_s|RD_t|WR_HILO,	0,		I1	},
+{"mult",    "7,s,t",	0x00000cbc, 0xfc003fff,	WR_a|RD_s|RD_t,		0,		D32	},
 {"multu",   "s,t",	0x00009b3c, 0xfc00ffff,	RD_s|RD_t|WR_HILO,	0,		I1	},
+{"multu",   "7,s,t",	0x00001cbc, 0xfc003fff,	WR_a|RD_s|RD_t,		0,		D32	},
 {"neg",     "d,w",	0x00000190, 0xfc1f07ff,	WR_d|RD_t,		0,		I1	}, /* sub 0 */
 {"negu",    "d,w",	0x000001d0, 0xfc1f07ff,	WR_d|RD_t,		0,		I1	}, /* subu 0 */
 {"neg.d",   "T,V",	0x54002b7b, 0xfc00ffff,	WR_T|RD_S|FP_D,		0,		I1	},
@@ -965,6 +983,160 @@ const struct mips_opcode micromips_opcodes[] =
 {"xor",     "d,v,t",	0x00000310, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,		0,		I1	},
 {"xori",    "t,r,i",	0x70000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
+/* MIPS DSP ASE.  */
+{"absq_s.ph", "t,s",	0x0000113c, 0xfc00ffff,	WR_t|RD_s,		0,		D32	},
+{"absq_s.w", "t,s",	0x0000213c, 0xfc00ffff,	WR_t|RD_s,		0,		D32	},
+{"addq.ph", "d,s,t",	0x0000000d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"addq_s.ph", "d,s,t",	0x0000040d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"addq_s.w", "d,s,t",	0x00000305, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"addsc",   "d,s,t",	0x00000385, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"addu.qb", "d,s,t",	0x000000cd, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"addu_s.qb", "d,s,t",	0x000004cd, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"addwc",   "d,s,t",	0x000003c5, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"bitrev",  "t,s",	0x0000313c, 0xfc00ffff,	WR_t|RD_s,		0,		D32	},
+{"bposge32", "p",	0x43600000, 0xffff0000,	CBD,			0,		D32	},
+{"cmp.eq.ph", "s,t",	0x00000005, 0xfc00ffff,	RD_s|RD_t,		0,		D32	},
+{"cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"cmp.le.ph", "s,t",	0x00000085, 0xfc00ffff,	RD_s|RD_t,		0,		D32	},
+{"cmpgu.le.qb", "d,s,t", 0x00000145, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"cmp.lt.ph", "s,t",	0x00000045, 0xfc00ffff,	RD_s|RD_t,		0,		D32	},
+{"cmpgu.lt.qb", "d,s,t", 0x00000105, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"cmpu.eq.qb", "s,t",	0x00000245, 0xfc00ffff,	RD_s|RD_t,		0,		D32	},
+{"cmpu.le.qb", "s,t",	0x000002c5, 0xfc00ffff,	RD_s|RD_t,		0,		D32	},
+{"cmpu.lt.qb", "s,t",	0x00000285, 0xfc00ffff,	RD_s|RD_t,		0,		D32	},
+{"dpaq_sa.l.w", "7,s,t", 0x000012bc, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"dpaq_s.w.ph", "7,s,t", 0x000002bc, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"dpau.h.qbl", "7,s,t", 0x000020bc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D32	},
+{"dpau.h.qbr", "7,s,t", 0x000030bc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D32	},
+{"dpsq_sa.l.w", "7,s,t", 0x000016bc, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"dpsq_s.w.ph", "7,s,t", 0x000006bc, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"dpsu.h.qbl", "7,s,t",	0x000024bc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D32	},
+{"dpsu.h.qbr", "7,s,t",	0x000034bc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D32	},
+{"extpdp",  "t,7,6",	0x0000367c, 0xfc003fff,	WR_t|RD_a|DSP_VOLA,	0,		D32	},
+{"extpdpv", "t,7,s",	0x000038bc, 0xfc003fff,	WR_t|RD_a|RD_s|DSP_VOLA, 0,		D32	},
+{"extp",    "t,7,6",	0x0000267c, 0xfc003fff,	WR_t|RD_a,		0,		D32	},
+{"extpv",   "t,7,s",	0x000028bc, 0xfc003fff,	WR_t|RD_a|RD_s,		0,		D32	},
+{"extr_rs.w", "t,7,6",	0x00002e7c, 0xfc003fff,	WR_t|RD_a,		0,		D32	},
+{"extr_r.w", "t,7,6",	0x00001e7c, 0xfc003fff,	WR_t|RD_a,		0,		D32	},
+{"extr_s.h", "t,7,6",	0x00003e7c, 0xfc003fff,	WR_t|RD_a,		0,		D32	},
+{"extrv_rs.w", "t,7,s",	0x00002ebc, 0xfc003fff,	WR_t|RD_a|RD_s,		0,		D32	},
+{"extrv_r.w", "t,7,s",	0x00001ebc, 0xfc003fff,	WR_t|RD_a|RD_s,		0,		D32	},
+{"extrv_s.h", "t,7,s",	0x00003ebc, 0xfc003fff,	WR_t|RD_a|RD_s,		0,		D32	},
+{"extrv.w", "t,7,s",	0x00000ebc, 0xfc003fff,	WR_t|RD_a|RD_s,		0,		D32	},
+{"extr.w",  "t,7,6",	0x00000e7c, 0xfc003fff,	WR_t|RD_a,		0,		D32	},
+{"insv",    "t,s",	0x0000413c, 0xfc00ffff,	WR_t|RD_s,		0,		D32	},
+{"lbux",    "d,t(b)",	0x00000225, 0xfc0007ff,	WR_d|RD_b|RD_t,		0,		D32	},
+{"lhx",     "d,t(b)",	0x00000165, 0xfc0007ff,	WR_d|RD_b|RD_t,		0,		D32	},
+{"lwx",     "d,t(b)",	0x000001a5, 0xfc0007ff,	WR_d|RD_b|RD_t,		0,		D32	},
+{"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"maq_s.w.phr", "7,s,t", 0x00000a7c, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"modsub",  "d,s,t",	0x00000295, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"mthlip",  "s,7",	0x0000027c, 0xffe03fff,	RD_s|MOD_a|DSP_VOLA,	0,		D32	},
+{"muleq_s.w.phl", "d,s,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
+{"muleq_s.w.phr", "d,s,t", 0x00000065, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
+{"muleu_s.ph.qbl", "d,s,t", 0x00000095, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
+{"muleu_s.ph.qbr", "d,s,t", 0x000000d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
+{"mulq_rs.ph", "d,s,t",	0x00000115, 0xfc0007ff,	WR_d|RD_s|RD_t|WR_HILO,	0,		D32	},
+{"mulsaq_s.w.ph", "7,s,t", 0x00003cbc, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D32	},
+{"packrl.ph", "d,s,t",	0x000001ad, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"pick.ph", "d,s,t",	0x0000022d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"pick.qb", "d,s,t",	0x000001ed, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"precequ.ph.qbla", "t,s", 0x0000733c, 0xfc00ffff, WR_t|RD_s,		0,		D32	},
+{"precequ.ph.qbl", "t,s", 0x0000713c, 0xfc00ffff, WR_t|RD_s,		0,		D32	},
+{"precequ.ph.qbra", "t,s", 0x0000933c, 0xfc00ffff, WR_t|RD_s,		0,		D32	},
+{"precequ.ph.qbr", "t,s", 0x0000913c, 0xfc00ffff, WR_t|RD_s,		0,		D32	},
+{"preceq.w.phl", "t,s",	0x0000513c, 0xfc00ffff,	WR_t|RD_s,		0,		D32	},
+{"preceq.w.phr", "t,s",	0x0000613c, 0xfc00ffff,	WR_t|RD_s,		0,		D32	},
+{"preceu.ph.qbla", "t,s", 0x0000b33c, 0xfc00ffff, WR_t|RD_s,		0,		D32	},
+{"preceu.ph.qbl", "t,s", 0x0000b13c, 0xfc00ffff, WR_t|RD_s,		0,		D32	},
+{"preceu.ph.qbra", "t,s",0x0000d33c, 0xfc00ffff, WR_t|RD_s,		0,		D32	},
+{"preceu.ph.qbr", "t,s", 0x0000d13c, 0xfc00ffff, WR_t|RD_s,		0,		D32	},
+{"precrq.ph.w", "d,s,t", 0x000000ed, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"precrq.qb.ph", "d,s,t", 0x000000ad, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"precrq_rs.ph.w", "d,s,t", 0x0000012d, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"precrqu_s.qb.ph", "d,s,t", 0x0000016d, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
+{"raddu.w.qb", "t,s",	0x0000f13c, 0xfc00ffff,	WR_t|RD_s,		0,		D32	},
+{"rddsp",   "t",	0x000fc67c, 0xfc1fffff,	WR_t,			0,		D32	},
+{"rddsp",   "t,8",	0x0000067c, 0xfc103fff,	WR_t,			0,		D32	},
+{"repl.ph", "d,@",	0x0000003d, 0xfc0007ff,	WR_d,			0,		D32	},
+{"repl.qb", "t,5",	0x000005fc, 0xfc001fff,	WR_t,			0,		D32	},
+{"replv.ph", "t,s",	0x0000033c, 0xfc00ffff,	WR_t|RD_s,		0,		D32	},
+{"replv.qb", "t,s",	0x0000133c, 0xfc00ffff,	WR_t|RD_s,		0,		D32	},
+{"shilo",   "7,0",	0x0000001d, 0xffc03fff,	MOD_a,			0,		D32	},
+{"shilov",  "7,s",	0x0000127c, 0xffe03fff,	MOD_a|RD_s,		0,		D32	},
+{"shll.ph", "t,s,4",	0x000003b5, 0xfc000fff,	WR_t|RD_s,		0,		D32	},
+{"shll.qb", "t,s,3",	0x0000087c, 0xfc001fff,	WR_t|RD_s,		0,		D32	},
+{"shll_s.ph", "t,s,4",	0x00000bb5, 0xfc000fff,	WR_t|RD_s,		0,		D32	},
+{"shll_s.w", "t,s,^",	0x000003f5, 0xfc0007ff,	WR_t|RD_s,		0,		D32	},
+{"shllv.ph", "d,t,s",	0x0000038d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"shllv.qb", "d,t,s",	0x00000395, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"shllv_s.ph", "d,t,s",	0x0000078d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"shllv_s.w", "d,t,s",	0x000003d5, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"shra.ph", "t,s,4",	0x00000335, 0xfc000fff,	WR_t|RD_s,		0,		D32	},
+{"shra_r.ph", "t,s,4",	0x00000735, 0xfc000fff,	WR_t|RD_s,		0,		D32	},
+{"shra_r.w", "t,s,^",	0x000002f5, 0xfc0007ff,	WR_t|RD_s,		0,		D32	},
+{"shrav.ph", "d,t,s",	0x0000018d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"shrav_r.ph", "d,t,s",	0x0000058d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"shrav_r.w", "d,t,s",	0x000002d5, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"shrl.qb", "t,s,3",	0x0000187c, 0xfc001fff,	WR_t|RD_s,		0,		D32	},
+{"shrlv.qb", "d,t,s",	0x00000355, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"subq.ph", "d,s,t",	0x0000020d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"subq_s.ph", "d,s,t",	0x0000060d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"subq_s.w", "d,s,t",	0x00000345, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"subu.qb", "d,s,t",	0x000002cd, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"subu_s.qb", "d,s,t",	0x000006cd, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D32	},
+{"wrdsp",   "t",	0x000fd67c, 0xfc1fffff,	RD_t|DSP_VOLA,		0,		D32	},
+{"wrdsp",   "t,8",	0x0000167c, 0xfc103fff,	RD_t|DSP_VOLA,		0,		D32	},
+/* MIPS DSP ASE Rev2.  */
+{"absq_s.qb", "t,s",	0x0000013c, 0xfc00ffff,	WR_t|RD_s,		0,		D33	},
+{"addqh.ph", "d,s,t",	0x0000004d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"addqh_r.ph", "d,s,t",	0x0000044d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"addqh.w", "d,s,t",	0x0000008d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"addqh_r.w", "d,s,t",	0x0000048d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"addu.ph", "d,s,t",	0x0000010d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"addu_s.ph", "d,s,t",	0x0000050d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"adduh.qb", "d,s,t",	0x0000014d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"adduh_r.qb", "d,s,t",	0x0000054d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"append",  "t,s,h",	0x00000215, 0xfc0007ff,	WR_t|RD_t|RD_s,		0,		D33	},
+{"balign",  "t,s,I",	0,    (int) M_BALIGN,	INSN_MACRO,		0,		D33	},
+{"balign",  "t,s,2",	0x000008bc, 0xfc003fff,	WR_t|RD_t|RD_s,		0,		D33	},
+{"cmpgdu.eq.qb", "d,s,t", 0x00000185, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D33	},
+{"cmpgdu.lt.qb", "d,s,t", 0x000001c5, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D33	},
+{"cmpgdu.le.qb", "d,s,t", 0x00000205, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D33	},
+{"dpa.w.ph", "7,s,t",	0x000000bc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D33	},
+{"dpaqx_s.w.ph", "7,s,t", 0x000022bc, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D33	},
+{"dpaqx_sa.w.ph", "7,s,t", 0x000032bc, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D33	},
+{"dpax.w.ph", "7,s,t",	0x000010bc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D33	},
+{"dps.w.ph", "7,s,t",	0x000004bc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D33	},
+{"dpsqx_s.w.ph", "7,s,t", 0x000026bc, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D33	},
+{"dpsqx_sa.w.ph", "7,s,t", 0x000036bc, 0xfc003fff, MOD_a|RD_s|RD_t,	0,		D33	},
+{"dpsx.w.ph", "7,s,t",	0x000014bc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D33	},
+{"mul.ph",  "d,s,t",	0x0000002d, 0xfc0007ff,	WR_d|RD_s|RD_t|WR_HILO,	0,		D33	},
+{"mul_s.ph", "d,s,t",	0x0000042d, 0xfc0007ff,	WR_d|RD_s|RD_t|WR_HILO,	0,		D33	},
+{"mulq_rs.w", "d,s,t",	0x00000195, 0xfc0007ff,	WR_d|RD_s|RD_t|WR_HILO,	0,		D33	},
+{"mulq_s.ph", "d,s,t",	0x00000155, 0xfc0007ff,	WR_d|RD_s|RD_t|WR_HILO,	0,		D33	},
+{"mulq_s.w", "d,s,t",	0x000001d5, 0xfc0007ff,	WR_d|RD_s|RD_t|WR_HILO,	0,		D33	},
+{"mulsa.w.ph", "7,s,t",	0x00002cbc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,		D33	},
+{"precr.qb.ph", "d,s,t", 0x0000006d, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D33	},
+{"precr_sra.ph.w", "t,s,h", 0x000003cd, 0xfc0007ff, WR_t|RD_t|RD_s,	0,		D33	},
+{"precr_sra_r.ph.w", "t,s,h", 0x000007cd, 0xfc0007ff, WR_t|RD_t|RD_s,	0,		D33	},
+{"prepend", "t,s,h",	0x00000255, 0xfc0007ff,	WR_t|RD_t|RD_s,		0,		D33	},
+{"shra.qb", "t,s,3",	0x000001fc, 0xfc001fff,	WR_t|RD_s,		0,		D33	},
+{"shra_r.qb", "t,s,3",	0x000011fc, 0xfc001fff,	WR_t|RD_s,		0,		D33	},
+{"shrav.qb", "d,t,s",	0x000001cd, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"shrav_r.qb", "d,t,s",	0x000005cd, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"shrl.ph", "t,s,4",	0x000003fc, 0xfc000fff,	WR_t|RD_s,		0,		D33	},
+{"shrlv.ph", "d,t,s",	0x00000315, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"subu.ph", "d,s,t",	0x0000030d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"subu_s.ph", "d,s,t",	0x0000070d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"subuh.qb", "d,s,t",	0x0000034d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"subuh_r.qb", "d,s,t",	0x0000074d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"subqh.ph", "d,s,t",	0x0000024d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"subqh_r.ph", "d,s,t",	0x0000064d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"subqh.w", "d,s,t",	0x0000028d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
+{"subqh_r.w", "d,s,t",	0x0000068d, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		D33	},
 };
 
 const int bfd_micromips_num_opcodes =