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| author | Michael Eager <eager@eagercon.com> | 2012-11-14 17:05:24 +0000 |
|---|---|---|
| committer | Michael Eager <eager@eagercon.com> | 2012-11-14 17:05:24 +0000 |
| commit | d3da77419a529a0af2c3e5109bebed65752bc52f (patch) | |
| tree | f243496979f4234e3783a6c5215a8cb3f0660e93 /opcodes/microblaze-opcm.h | |
| parent | ed8ec0ec784e7e2fd114f4a14e2751add8942c9c (diff) | |
| download | gdb-d3da77419a529a0af2c3e5109bebed65752bc52f.zip gdb-d3da77419a529a0af2c3e5109bebed65752bc52f.tar.gz gdb-d3da77419a529a0af2c3e5109bebed65752bc52f.tar.bz2 | |
opcodes/
* microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
and increase MAX_OPCODES.
(op_code_struct): add mbar and sleep
* microblaze-opcm.h (microblaze_instr): add mbar
Define IMM_MBAR and IMM5_MBAR_MASK
* microblaze-dis.c: Add get_field_imm5_mbar
(print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
gas/
* config/tc-microblaze.c (md_assemble): Add support for INST_TYPE_IMM5
gas/testsuite/
* gas/microblaze/allinsn.s: Add mbar and sleep
* gas/microblaze/allinsn.d: Likewise
Diffstat (limited to 'opcodes/microblaze-opcm.h')
| -rw-r--r-- | opcodes/microblaze-opcm.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h index 58e6fd4..867263e 100644 --- a/opcodes/microblaze-opcm.h +++ b/opcodes/microblaze-opcm.h @@ -31,7 +31,7 @@ enum microblaze_instr idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor, andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, - wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd, + wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, @@ -122,6 +122,7 @@ enum microblaze_instr_type #define RA_LOW 16 /* Low bit for RA. */ #define RB_LOW 11 /* Low bit for RB. */ #define IMM_LOW 0 /* Low bit for immediate. */ +#define IMM_MBAR 21 /* low bit for mbar instruction. */ #define RD_MASK 0x03E00000 #define RA_MASK 0x001F0000 @@ -131,6 +132,9 @@ enum microblaze_instr_type /* Imm mask for barrel shifts. */ #define IMM5_MASK 0x0000001F +/* Imm mask for mbar. */ +#define IMM5_MBAR_MASK 0x03E00000 + /* FSL imm mask for get, put instructions. */ #define RFSL_MASK 0x000000F |