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| author | Michael Eager <eager@eagercon.com> | 2012-11-14 17:05:24 +0000 |
|---|---|---|
| committer | Michael Eager <eager@eagercon.com> | 2012-11-14 17:05:24 +0000 |
| commit | d3da77419a529a0af2c3e5109bebed65752bc52f (patch) | |
| tree | f243496979f4234e3783a6c5215a8cb3f0660e93 /opcodes/microblaze-opc.h | |
| parent | ed8ec0ec784e7e2fd114f4a14e2751add8942c9c (diff) | |
| download | gdb-d3da77419a529a0af2c3e5109bebed65752bc52f.zip gdb-d3da77419a529a0af2c3e5109bebed65752bc52f.tar.gz gdb-d3da77419a529a0af2c3e5109bebed65752bc52f.tar.bz2 | |
opcodes/
* microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
and increase MAX_OPCODES.
(op_code_struct): add mbar and sleep
* microblaze-opcm.h (microblaze_instr): add mbar
Define IMM_MBAR and IMM5_MBAR_MASK
* microblaze-dis.c: Add get_field_imm5_mbar
(print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
gas/
* config/tc-microblaze.c (md_assemble): Add support for INST_TYPE_IMM5
gas/testsuite/
* gas/microblaze/allinsn.s: Add mbar and sleep
* gas/microblaze/allinsn.d: Likewise
Diffstat (limited to 'opcodes/microblaze-opc.h')
| -rw-r--r-- | opcodes/microblaze-opc.h | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h index 132b951..0447fc5 100644 --- a/opcodes/microblaze-opc.h +++ b/opcodes/microblaze-opc.h @@ -56,6 +56,9 @@ /* New insn type for t*put. */ #define INST_TYPE_RFSL 19 +/* For mbar. */ +#define INST_TYPE_IMM5 20 + #define INST_TYPE_NONE 25 @@ -76,8 +79,8 @@ #define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */ #define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */ #define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits. */ -#define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last - nibble of last byte for spr. */ +#define OPCODE_MASK_H13S 0xFFE0E7F0 /* High 11 16:18 21:27 bits, 19:20 bits + and last nibble of last byte for spr. */ #define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last nibble of last byte for spr. */ #define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits. */ @@ -92,11 +95,13 @@ /* New Mask for msrset, msrclr insns. */ #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ +/* Mask for mbar insn. */ +#define OPCODE_MASK_HN 0xFF020004 /* High 16 bits and bits 14, 29. */ #define DELAY_SLOT 1 #define NO_DELAY_SLOT 0 -#define MAX_OPCODES 285 +#define MAX_OPCODES 287 struct op_code_struct { @@ -395,6 +400,8 @@ struct op_code_struct {"necaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd, anyware_inst }, {"tnecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst }, {"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst }, + {"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst }, + {"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */ {"", 0, 0, 0, 0, 0, 0, 0, 0}, }; @@ -412,5 +419,8 @@ char pvr_register_prefix[] = "rpvr"; #define MIN_IMM15 ((int) 0x0000) #define MAX_IMM15 ((int) 0x7fff) +#define MIN_IMM5 ((int) 0x00000000) +#define MAX_IMM5 ((int) 0x0000001f) + #endif /* MICROBLAZE_OPC */ |