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authorDJ Delorie <dj@redhat.com>2009-04-30 21:23:30 +0000
committerDJ Delorie <dj@redhat.com>2009-04-30 21:23:30 +0000
commit3526b6802eb19481fc9143f53246640e77e3198a (patch)
treee9c3bce3f605f05f95f5d40a1507d0357a176ca9 /opcodes/mep-desc.h
parent4e38f72c0f2872a2fbbee5619009e572cf1338dc (diff)
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Index: opcodes
* mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate. Index: gas * config/tc-mep.c (md_begin): Check coprocessor type. (md_check_parallel64_scheduling): Use memset to initialize the buffer. (md_check_parallel32_scheduling): Likewise. (slot_ok): New. (mep_check_ivc2_scheduling): New. (mep_check_parallel_scheduling): Call it. (mep_process_saved_insns): Add IVC2 slot support. (md_assemble): Likewise.
Diffstat (limited to 'opcodes/mep-desc.h')
-rw-r--r--opcodes/mep-desc.h50
1 files changed, 42 insertions, 8 deletions
diff --git a/opcodes/mep-desc.h b/opcodes/mep-desc.h
index b4de4d5..19832e0 100644
--- a/opcodes/mep-desc.h
+++ b/opcodes/mep-desc.h
@@ -51,7 +51,7 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger.
#define CGEN_INT_INSN_P 1
/* Maximum number of syntax elements in an instruction. */
-#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 18
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
@@ -59,7 +59,7 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger.
#define CGEN_MNEMONIC_OPERANDS
/* Maximum number of fields in an instruction. */
-#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10
/* Enums. */
@@ -81,7 +81,8 @@ typedef enum mach_attr {
/* Enum declaration for instruction set selection. */
typedef enum isa_attr {
- ISA_MEP, ISA_EXT_CORE1, ISA_MAX
+ ISA_MEP, ISA_EXT_CORE1, ISA_EXT_COP1_16, ISA_EXT_COP1_32
+ , ISA_EXT_COP1_48, ISA_EXT_COP1_64, ISA_MAX
} ISA_ATTR;
/* Enum declaration for datatype to use for C intrinsics mapping. */
@@ -96,6 +97,12 @@ typedef enum config_attr {
CONFIG_NONE, CONFIG_DEFAULT
} CONFIG_ATTR;
+/* Enum declaration for slots for which this opcode is valid - c3, p0s, p0, p1. */
+typedef enum slots_attr {
+ SLOTS_CORE, SLOTS_C3, SLOTS_P0S, SLOTS_P0
+ , SLOTS_P1
+} SLOTS_ATTR;
+
/* Number of architecture variants. */
#define MAX_ISAS ((int) ISA_MAX)
#define MAX_MACHS ((int) MACH_MAX)
@@ -151,7 +158,20 @@ typedef enum ifield_type {
, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_C5N4, MEP_F_C5N5
, MEP_F_C5N6, MEP_F_C5N7, MEP_F_RL5, MEP_F_12S20
, MEP_F_C5_RNM, MEP_F_C5_RM, MEP_F_C5_16U16, MEP_F_C5_RMUIMM20
- , MEP_F_C5_RNMUIMM24, MEP_F_MAX
+ , MEP_F_C5_RNMUIMM24, MEP_F_IVC2_2U4, MEP_F_IVC2_3U4, MEP_F_IVC2_8U4
+ , MEP_F_IVC2_8S4, MEP_F_IVC2_1U6, MEP_F_IVC2_2U6, MEP_F_IVC2_3U6
+ , MEP_F_IVC2_6U6, MEP_F_IVC2_5U7, MEP_F_IVC2_4U8, MEP_F_IVC2_3U9
+ , MEP_F_IVC2_5U16, MEP_F_IVC2_5U21, MEP_F_IVC2_5U26, MEP_F_IVC2_1U31
+ , MEP_F_IVC2_4U16, MEP_F_IVC2_4U20, MEP_F_IVC2_4U24, MEP_F_IVC2_4U28
+ , MEP_F_IVC2_2U0, MEP_F_IVC2_3U0, MEP_F_IVC2_4U0, MEP_F_IVC2_5U0
+ , MEP_F_IVC2_8U0, MEP_F_IVC2_8S0, MEP_F_IVC2_6U2, MEP_F_IVC2_5U3
+ , MEP_F_IVC2_4U4, MEP_F_IVC2_3U5, MEP_F_IVC2_5U8, MEP_F_IVC2_4U10
+ , MEP_F_IVC2_3U12, MEP_F_IVC2_5U13, MEP_F_IVC2_2U18, MEP_F_IVC2_5U18
+ , MEP_F_IVC2_8U20, MEP_F_IVC2_8S20, MEP_F_IVC2_5U23, MEP_F_IVC2_2U23
+ , MEP_F_IVC2_3U25, MEP_F_IVC2_IMM16P0, MEP_F_IVC2_SIMM16P0, MEP_F_IVC2_CRN
+ , MEP_F_IVC2_CRM, MEP_F_IVC2_CCRN_H1, MEP_F_IVC2_CCRN_H2, MEP_F_IVC2_CCRN_LO
+ , MEP_F_IVC2_CMOV1, MEP_F_IVC2_CMOV2, MEP_F_IVC2_CMOV3, MEP_F_IVC2_CCRN
+ , MEP_F_IVC2_CRNX, MEP_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) MEP_F_MAX)
@@ -181,7 +201,8 @@ typedef enum cgen_hw_attr {
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
, HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR
- , HW_H_CR64, HW_H_CR, HW_H_CCR, HW_MAX
+ , HW_H_CR64, HW_H_CR64_W, HW_H_CR, HW_H_CCR
+ , HW_H_CCR_W, HW_H_CR_IVC2, HW_H_CCR_IVC2, HW_MAX
} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
@@ -236,11 +257,21 @@ typedef enum cgen_operand_type {
, MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
, MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP10, MEP_OPERAND_CDISP10A2, MEP_OPERAND_CDISP10A4
, MEP_OPERAND_CDISP10A8, MEP_OPERAND_ZERO, MEP_OPERAND_RL5, MEP_OPERAND_CDISP12
- , MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_MAX
+ , MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_CROC
+ , MEP_OPERAND_CRQC, MEP_OPERAND_CRPC, MEP_OPERAND_IVC_X_6_1, MEP_OPERAND_IVC_X_6_2
+ , MEP_OPERAND_IVC_X_6_3, MEP_OPERAND_IMM3P4, MEP_OPERAND_IMM3P9, MEP_OPERAND_IMM4P8
+ , MEP_OPERAND_IMM5P7, MEP_OPERAND_IMM6P6, MEP_OPERAND_IMM8P4, MEP_OPERAND_SIMM8P4
+ , MEP_OPERAND_IMM3P5, MEP_OPERAND_IMM3P12, MEP_OPERAND_IMM4P4, MEP_OPERAND_IMM4P10
+ , MEP_OPERAND_IMM5P8, MEP_OPERAND_IMM5P3, MEP_OPERAND_IMM6P2, MEP_OPERAND_IMM5P23
+ , MEP_OPERAND_IMM3P25, MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_IMM8P20
+ , MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP, MEP_OPERAND_IVC_X_0_2
+ , MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5, MEP_OPERAND_IMM16P0
+ , MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN, MEP_OPERAND_IVC2CCRN
+ , MEP_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
-#define MAX_OPERANDS 83
+#define MAX_OPERANDS 120
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
@@ -258,7 +289,7 @@ typedef enum cgen_insn_attr {
, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP
, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE
, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
- , CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
@@ -269,6 +300,7 @@ typedef enum cgen_insn_attr {
#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_SLOTS_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SLOTS-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
@@ -320,6 +352,8 @@ extern CGEN_KEYWORD mep_cgen_opval_h_csr;
extern CGEN_KEYWORD mep_cgen_opval_h_cr64;
extern CGEN_KEYWORD mep_cgen_opval_h_cr;
extern CGEN_KEYWORD mep_cgen_opval_h_ccr;
+extern CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2;
+extern CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2;
extern const CGEN_HW_ENTRY mep_cgen_hw_table[];