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| author | Doug Evans <dje@google.com> | 2003-06-10 22:08:45 +0000 |
|---|---|---|
| committer | Doug Evans <dje@google.com> | 2003-06-10 22:08:45 +0000 |
| commit | b11dcf4e7fcf7ef8557487744250b5ea27b71b9c (patch) | |
| tree | bb9cd38e3ca5c32128af015c3cfe45b5f0c5efb6 /opcodes/m32r-opc.c | |
| parent | 5b5b78dacbb201872ab6442f3ea5faeb73f399df (diff) | |
| download | gdb-b11dcf4e7fcf7ef8557487744250b5ea27b71b9c.zip gdb-b11dcf4e7fcf7ef8557487744250b5ea27b71b9c.tar.gz gdb-b11dcf4e7fcf7ef8557487744250b5ea27b71b9c.tar.bz2 | |
opcodes:
* cgen-asm.in (@arch@_cgen_assemble_insn): CGEN_INSN_RELAX renamed to
CGEN_INSN_RELAXED.
* fr30-asm.c,fr30-desc.c,fr30-desc.h: Regenerate.
* frv-asm.c,frv-desc.c,frv-desc.h: Regenerate.
* ip2k-asm.c,ip2k-desc.c,ip2k-desc.h: Regenerate.
* iq2000-asm.c,iq2000-desc.c,iq2000-desc.h: Regenerate.
* m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-opc.c: Regenerate.
* openrisc-asm.c,openrisc-desc.c,openrisc-desc.h: Regenerate.
* xstormy16-asm.c,xstormy16-desc.c,xstormy16-desc.h: Regenerate.
gas:
* cgen.c (gas_cgen_finish_insn): CGEN_INSN_RELAX renamed to
CGEN_INSN_RELAXED.
* config/tc-fr30.c (md_estimate_size_before_relax): Ditto.
* config/tc-m32r.c (md_estimate_size_before_relax): Ditto.
* config/tc-openrisc.c (md_estimate_size_before_relax): Ditto.
Diffstat (limited to 'opcodes/m32r-opc.c')
| -rw-r--r-- | opcodes/m32r-opc.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c index b60c1bf..8143b61 100644 --- a/opcodes/m32r-opc.c +++ b/opcodes/m32r-opc.c @@ -1187,7 +1187,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bc $disp24 */ { -1, "bc24r", "bc", 32, - { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, /* bl $disp8 */ { @@ -1197,7 +1197,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bl $disp24 */ { -1, "bl24r", "bl", 32, - { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, /* bcl $disp8 */ { @@ -1207,7 +1207,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bcl $disp24 */ { -1, "bcl24r", "bcl", 32, - { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } }, /* bnc $disp8 */ { @@ -1217,7 +1217,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bnc $disp24 */ { -1, "bnc24r", "bnc", 32, - { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, /* bra $disp8 */ { @@ -1227,7 +1227,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bra $disp24 */ { -1, "bra24r", "bra", 32, - { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, /* bncl $disp8 */ { @@ -1237,7 +1237,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bncl $disp24 */ { -1, "bncl24r", "bncl", 32, - { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } }, /* ld $dr,@($sr) */ { |