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| author | Nick Clifton <nickc@redhat.com> | 2003-12-03 17:38:48 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2003-12-03 17:38:48 +0000 |
| commit | 8884595866edbe6697a1268f5605b7ffe91efb0a (patch) | |
| tree | 1710b68cb96d5cba8449135a5113d5c9a6a8c62f /opcodes/m32r-dis.c | |
| parent | f8fc3443814cb6f315680a7fb34ff4effc86442e (diff) | |
| download | gdb-8884595866edbe6697a1268f5605b7ffe91efb0a.zip gdb-8884595866edbe6697a1268f5605b7ffe91efb0a.tar.gz gdb-8884595866edbe6697a1268f5605b7ffe91efb0a.tar.bz2 | |
Add support for the M32R2 processor.
Diffstat (limited to 'opcodes/m32r-dis.c')
| -rw-r--r-- | opcodes/m32r-dis.c | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index e8abbc6..6e5ea70 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -100,6 +100,8 @@ my_print_insn (cd, pc, info) char *buf = buffer; int status; int buflen = (pc & 3) == 0 ? 4 : 2; + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; + char *x; /* Read the base part of the insn. */ @@ -111,22 +113,25 @@ my_print_insn (cd, pc, info) } /* 32 bit insn? */ - if ((pc & 3) == 0 && (buf[0] & 0x80) != 0) + x = (big_p ? &buf[0] : &buf[3]); + if ((pc & 3) == 0 && (*x & 0x80) != 0) return print_insn (cd, pc, info, buf, buflen); /* Print the first insn. */ + buf += (big_p ? 0 : 2); if ((pc & 3) == 0) { if (print_insn (cd, pc, info, buf, 2) == 0) (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - buf += 2; } + buf += (big_p ? 2 : -2); - if (buf[0] & 0x80) + x = (big_p ? &buf[0] : &buf[1]); + if (*x & 0x80) { /* Parallel. */ (*info->fprintf_func) (info->stream, " || "); - buf[0] &= 0x7f; + *x &= 0x7f; } else (*info->fprintf_func) (info->stream, " -> "); @@ -235,12 +240,18 @@ m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) case M32R_OPERAND_UIMM24 : print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); break; + case M32R_OPERAND_UIMM3 : + print_normal (cd, info, fields->f_uimm3, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; case M32R_OPERAND_UIMM4 : print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); break; case M32R_OPERAND_UIMM5 : print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); break; + case M32R_OPERAND_UIMM8 : + print_normal (cd, info, fields->f_uimm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; case M32R_OPERAND_ULO16 : print_normal (cd, info, fields->f_uimm16, 0, pc, length); break; |