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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-10 19:20:05 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-15 13:11:48 +0000 |
| commit | 42fd649404afce3c36337d2af1f07836eb4bdcc2 (patch) | |
| tree | 3b4e1f61f1bdb637b7a9c6fcd077ffbae70338e1 /opcodes/m32r-asm.c | |
| parent | e771eaf8bb4cfc4a04346a14756fa21e01e7b9ba (diff) | |
| download | gdb-42fd649404afce3c36337d2af1f07836eb4bdcc2.zip gdb-42fd649404afce3c36337d2af1f07836eb4bdcc2.tar.gz gdb-42fd649404afce3c36337d2af1f07836eb4bdcc2.tar.bz2 | |
aarch64: rcpc3: Add FP load/store insns
Along with the relevant unit-tests, this adds the following rcpc3
instructions:
STL1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAP1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAPUR <Bt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Ht>, [<Xn|SP>{, #<simm>}]
LDAPUR <St>, [<Xn|SP>{, #<simm>}]
LDAPUR <Dt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Qt>, [<Xn|SP>{, #<simm>}]
STLUR <Bt>, [<Xn|SP>{, #<simm>}]
STLUR <Ht>, [<Xn|SP>{, #<simm>}]
STLUR <St>, [<Xn|SP>{, #<simm>}]
STLUR <Dt>, [<Xn|SP>{, #<simm>}]
STLUR <Qt>, [<Xn|SP>{, #<simm>}]
with `#<simm>' taking on a signed 8-bit integer value in the range
[-256,255] and `index' the values 0 or 1.
Co-authored-by: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Diffstat (limited to 'opcodes/m32r-asm.c')
0 files changed, 0 insertions, 0 deletions