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| author | DJ Delorie <dj@redhat.com> | 2005-10-25 18:52:02 +0000 |
|---|---|---|
| committer | DJ Delorie <dj@redhat.com> | 2005-10-25 18:52:02 +0000 |
| commit | 92e0a9414cfe5bc3f1ec72a2ff1fae5b8838845b (patch) | |
| tree | 6949f9422509b84b7b4664a87e2a03e082698fbb /opcodes/m32c-opc.c | |
| parent | b7b8fb1dfa651aa037c5b22df89e4356dfabd9e0 (diff) | |
| download | gdb-92e0a9414cfe5bc3f1ec72a2ff1fae5b8838845b.zip gdb-92e0a9414cfe5bc3f1ec72a2ff1fae5b8838845b.tar.gz gdb-92e0a9414cfe5bc3f1ec72a2ff1fae5b8838845b.tar.bz2 | |
* m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by
making one a macro of the other.
* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
Diffstat (limited to 'opcodes/m32c-opc.c')
| -rw-r--r-- | opcodes/m32c-opc.c | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/opcodes/m32c-opc.c b/opcodes/m32c-opc.c index 2ca538e..1ac8859 100644 --- a/opcodes/m32c-opc.c +++ b/opcodes/m32c-opc.c @@ -7497,7 +7497,7 @@ static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Un 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } }; -static const CGEN_IFMT ifmt_add16_Q_sp ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_add16_wQ_sp ATTRIBUTE_UNUSED = { 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } } }; @@ -78714,11 +78714,11 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (DSP_16_U16), 0 } }, & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ff0000 } }, -/* add${size}$Q #${Imm-12-s4},sp */ +/* add.w$Q #${Imm-12-s4},sp */ { { 0, 0, 0, 0 }, - { { MNEM, OP (SIZE), OP (Q), ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } }, - & ifmt_add16_Q_sp, { 0x7db0 } + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } }, + & ifmt_add16_wQ_sp, { 0x7db0 } }, /* add.b$G #${Imm-16-QI},sp */ { @@ -79682,6 +79682,10 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = #else #define F(f) & m32c_cgen_ifld_table[M32C_/**/f] #endif +static const CGEN_IFMT ifmt_add16_bQ_sp ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } } +}; + #undef F /* Each non-simple macro entry points to an array of expansion possibilities. */ @@ -79703,12 +79707,23 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = static const CGEN_IBASE m32c_cgen_macro_insn_table[] = { +/* add.b:q #${Imm-12-s4},sp */ + { + -1, "add16-bQ-sp", "add.b:q", 16, + { 0|A(ALIAS), { (1<<MACH_BASE), (1<<ISA_M16C) } } + }, }; /* The macro instruction opcode table. */ static const CGEN_OPCODE m32c_cgen_macro_insn_opcode_table[] = { +/* add.b:q #${Imm-12-s4},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } }, + & ifmt_add16_bQ_sp, { 0x7db0 } + }, }; #undef A |