* m10300-opc.c: Reorder more instructions so that we do not

        accidentally match a mn10300 instruction when we really
        wanted an am33 instruction.

1 files changed, 46 insertions, 33 deletions

diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c
index 4ff1512..3989c90 100644
--- a/opcodes/m10300-opc.c
+++ b/opcodes/m10300-opc.c
@@ -377,46 +377,34 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "mov",	0x70,	     0xf0,	  FMT_S0, 0,	{MEM(AM0), DN1}},
 { "mov",	0x5800,	     0xfcff,	  FMT_S1, 0,	{MEM(SP), DN0}},
 { "mov",	0x300000,    0xfc0000,    FMT_S2, 0,	{MEM(IMM16_MEM), DN0}},
-{ "mov",	0xfca40000,  0xfffc0000,  FMT_D4, 0,	{MEM(IMM32_MEM), DN0}},
 { "mov",	0xf000,	     0xfff0,	  FMT_D0, 0,	{MEM(AM0), AN1}},
 { "mov",	0x5c00,	     0xfcff,	  FMT_S1, 0,	{MEM(SP), AN0}},
 { "mov",	0xfaa00000,  0xfffc0000,  FMT_D2, 0,	{MEM(IMM16_MEM), AN0}},
-{ "mov",	0xfca00000,  0xfffc0000,  FMT_D4, 0,	{MEM(IMM32_MEM), AN0}},
 { "mov",	0x60,	     0xf0,	  FMT_S0, 0,	{DM1, MEM(AN0)}},
 { "mov",	0x4200,	     0xf3ff,	  FMT_S1, 0,	{DM1, MEM(SP)}},
 { "mov",	0x010000,    0xf30000,    FMT_S2, 0,	{DM1, MEM(IMM16_MEM)}},
-{ "mov",	0xfc810000,  0xfff30000,  FMT_D4, 0,	{DM1, MEM(IMM32_MEM)}},
 { "mov",	0xf010,	     0xfff0,	  FMT_D0, 0,	{AM1, MEM(AN0)}},
 { "mov",	0x4300,	     0xf3ff,	  FMT_S1, 0,	{AM1, MEM(SP)}},
 { "mov",	0xfa800000,  0xfff30000,  FMT_D2, 0,	{AM1, MEM(IMM16_MEM)}},
-{ "mov",	0xfc800000,  0xfff30000,  FMT_D4, 0,	{AM1, MEM(IMM32_MEM)}},
 { "mov",	0x5c00,	     0xfc00,	  FMT_S1, 0,	{MEM2(IMM8, SP), AN0}},
 { "mov",	0xf80000,    0xfff000,    FMT_D1, 0,	{MEM2(SD8, AM0), DN1}},
 { "mov",	0xfa000000,  0xfff00000,  FMT_D2, 0,	{MEM2(SD16, AM0), DN1}},
-{ "mov",	0xfc000000,  0xfff00000,  FMT_D4, 0,	{MEM2(IMM32,AM0), DN1}},
 { "mov",	0x5800,	     0xfc00,	  FMT_S1, 0,	{MEM2(IMM8, SP), DN0}},
 { "mov",	0xfab40000,  0xfffc0000,  FMT_D2, 0,	{MEM2(IMM16, SP), DN0}},
-{ "mov",	0xfcb40000,  0xfffc0000,  FMT_D4, 0,	{MEM2(IMM32, SP), DN0}},
 { "mov",	0xf300,	     0xffc0,	  FMT_D0, 0,	{MEM2(DI, AM0), DN2}},
 { "mov",	0xf82000,    0xfff000,    FMT_D1, 0,	{MEM2(SD8,AM0), AN1}},
 { "mov",	0xfa200000,  0xfff00000,  FMT_D2, 0,	{MEM2(SD16, AM0), AN1}},
-{ "mov",	0xfc200000,  0xfff00000,  FMT_D4, 0,	{MEM2(IMM32,AM0), AN1}},
 { "mov",	0xfab00000,  0xfffc0000,  FMT_D2, 0,	{MEM2(IMM16, SP), AN0}},
-{ "mov",	0xfcb00000,  0xfffc0000,  FMT_D4, 0,	{MEM2(IMM32, SP), AN0}},
 { "mov",	0xf380,	     0xffc0,	  FMT_D0, 0,	{MEM2(DI, AM0), AN2}},
 { "mov",	0x4300,	     0xf300,	  FMT_S1, 0,	{AM1, MEM2(IMM8, SP)}},
 { "mov",	0xf81000,    0xfff000,    FMT_D1, 0,	{DM1, MEM2(SD8, AN0)}},
 { "mov",	0xfa100000,  0xfff00000,  FMT_D2, 0,	{DM1, MEM2(SD16, AN0)}},
-{ "mov",	0xfc100000,  0xfff00000,  FMT_D4, 0,	{DM1, MEM2(IMM32,AN0)}},
 { "mov",	0x4200,	     0xf300,	  FMT_S1, 0,	{DM1, MEM2(IMM8, SP)}},
 { "mov",	0xfa910000,  0xfff30000,  FMT_D2, 0,	{DM1, MEM2(IMM16, SP)}},
-{ "mov",	0xfc910000,  0xfff30000,  FMT_D4, 0,	{DM1, MEM2(IMM32, SP)}},
 { "mov",	0xf340,	     0xffc0,	  FMT_D0, 0,	{DM2, MEM2(DI, AN0)}},
 { "mov",	0xf83000,    0xfff000,    FMT_D1, 0,	{AM1, MEM2(SD8, AN0)}},
 { "mov",	0xfa300000,  0xfff00000,  FMT_D2, 0,	{AM1, MEM2(SD16, AN0)}},
-{ "mov",	0xfc300000,  0xfff00000,  FMT_D4, 0,	{AM1, MEM2(IMM32,AN0)}},
 { "mov",	0xfa900000,  0xfff30000,  FMT_D2, 0,	{AM1, MEM2(IMM16, SP)}},
-{ "mov",	0xfc900000,  0xfff30000,  FMT_D4, 0,	{AM1, MEM2(IMM32, SP)}},
 { "mov",	0xf3c0,	     0xffc0,	  FMT_D0, 0,	{AM2, MEM2(DI, AN0)}},
 
 /* start-sanitize-am33 */
@@ -441,32 +429,20 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "mov",	0xf96a00,    0xffff00,    FMT_D6, AM33,	{MEMINC(RM0), RN2}},
 { "mov",	0xfb0e0000,  0xffff0f00,  FMT_D7, AM33,	{MEM(IMM8_MEM), RN2}},
 { "mov",	0xfd0e0000,  0xffff0f00,  FMT_D8, AM33,	{MEM(IMM24_MEM), RN2}},
-{ "mov",	0xfe0e0000,  0xffff0f00,  FMT_D9, AM33,	{MEM(IMM32_HIGH8_MEM),
-							 RN2}},
 { "mov",	0xf91a00,    0xffff00,    FMT_D6, AM33,	{RM2, MEM(RN0)}},
 { "mov",	0xf99a00,    0xffff0f,    FMT_D6, AM33,	{RM2, MEM(SP)}},
 { "mov",	0xf97a00,    0xffff00,    FMT_D6, AM33,	{RM2, MEMINC(RN0)}},
 { "mov",	0xfb1e0000,  0xffff0f00,  FMT_D7, AM33,	{RM2, MEM(IMM8_MEM)}},
 { "mov",	0xfd1e0000,  0xffff0f00,  FMT_D8, AM33,	{RM2, MEM(IMM24_MEM)}},
-{ "mov",	0xfe1e0000,  0xffff0f00,  FMT_D9, AM33,	{RM2,
-							 MEM(IMM32_HIGH8_MEM)}},
 { "mov",	0xfb0a0000,  0xffff0000,  FMT_D7, AM33,	{MEM2(SD8, RM0), RN2}},
 { "mov",	0xfd0a0000,  0xffff0000,  FMT_D8, AM33,	{MEM2(SD24, RM0), RN2}},
-{ "mov",	0xfe0a0000,  0xffff0000,  FMT_D9, AM33,	{MEM2(IMM32_HIGH8,RM0),
-							 RN2}},
 { "mov",	0xfb8e0000,  0xffff000f,  FMT_D7, AM33,	{MEM2(RI, RM0), RD2}},
 { "mov",	0xfb1a0000,  0xffff0000,  FMT_D7, AM33,	{RM2, MEM2(SD8, RN0)}},
 { "mov",	0xfd1a0000,  0xffff0000,  FMT_D8, AM33,	{RM2, MEM2(SD24, RN0)}},
-{ "mov",	0xfe1a0000,  0xffff0000,  FMT_D9, AM33,	{RM2, MEM2(IMM32_HIGH8,
-								   RN0)}},
 { "mov",	0xfb8a0000,  0xffff0f00,  FMT_D7, AM33,	{MEM2(SD8, SP), RN2}},
 { "mov",	0xfd8a0000,  0xffff0f00,  FMT_D8, AM33,	{MEM2(SD24, SP), RN2}},
-{ "mov",	0xfe8a0000,  0xffff0f00,  FMT_D9, AM33,	{MEM2(IMM32_HIGH8, SP),
-							 RN2}},
 { "mov",	0xfb9a0000,  0xffff0f00,  FMT_D7, AM33,	{RM2, MEM2(SD8, SP)}},
 { "mov",	0xfd9a0000,  0xffff0f00,  FMT_D8, AM33,	{RM2, MEM2(SD24, SP)}},
-{ "mov",	0xfe9a0000,  0xffff0f00,  FMT_D9, AM33,	{RM2, MEM2(IMM32_HIGH8, 
-								   SP)}},
 { "mov",	0xfb9e0000,  0xffff000f,  FMT_D7, AM33,	{RD2, MEM2(RI, RN0)}},
 /* end-sanitize-am33 */
 /* These must come after most of the other move instructions to avoid matching
@@ -475,6 +451,18 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "mov",	0xfccc0000,  0xfffc0000,  FMT_D4, 0,	{IMM32, DN0}},
 { "mov",	0x240000,    0xfc0000,    FMT_S2, 0,	{IMM16, AN0}},
 { "mov",	0xfcdc0000,  0xfffc0000,  FMT_D4, 0,	{IMM32, AN0}},
+{ "mov",	0xfca40000,  0xfffc0000,  FMT_D4, 0,	{MEM(IMM32_MEM), DN0}},
+{ "mov",	0xfca00000,  0xfffc0000,  FMT_D4, 0,	{MEM(IMM32_MEM), AN0}},
+{ "mov",	0xfc810000,  0xfff30000,  FMT_D4, 0,	{DM1, MEM(IMM32_MEM)}},
+{ "mov",	0xfc800000,  0xfff30000,  FMT_D4, 0,	{AM1, MEM(IMM32_MEM)}},
+{ "mov",	0xfc000000,  0xfff00000,  FMT_D4, 0,	{MEM2(IMM32,AM0), DN1}},
+{ "mov",	0xfcb40000,  0xfffc0000,  FMT_D4, 0,	{MEM2(IMM32, SP), DN0}},
+{ "mov",	0xfc200000,  0xfff00000,  FMT_D4, 0,	{MEM2(IMM32,AM0), AN1}},
+{ "mov",	0xfcb00000,  0xfffc0000,  FMT_D4, 0,	{MEM2(IMM32, SP), AN0}},
+{ "mov",	0xfc100000,  0xfff00000,  FMT_D4, 0,	{DM1, MEM2(IMM32,AN0)}},
+{ "mov",	0xfc910000,  0xfff30000,  FMT_D4, 0,	{DM1, MEM2(IMM32, SP)}},
+{ "mov",	0xfc300000,  0xfff00000,  FMT_D4, 0,	{AM1, MEM2(IMM32,AN0)}},
+{ "mov",	0xfc900000,  0xfff30000,  FMT_D4, 0,	{AM1, MEM2(IMM32, SP)}},
 /* These non-promoting variants need to come after all the other memory
    moves.  */
 { "mov",	0xf8f000,    0xfffc00,    FMT_D1, 0,	{MEM2(SD8N, AM0), SP}},
@@ -488,6 +476,18 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "mov",	0xfbf80000,  0xffff0000, FMT_D7, AM33,	{SIMM8, XRN02}},
 { "mov",	0xfdf80000,  0xffff0000, FMT_D8, AM33,	{SIMM24, XRN02}},
 { "mov",	0xfef80000,  0xffff0000, FMT_D9, AM33,	{IMM32_HIGH8, XRN02}},
+{ "mov",	0xfe0e0000,  0xffff0f00,  FMT_D9, AM33,	{MEM(IMM32_HIGH8_MEM),
+							 RN2}},
+{ "mov",	0xfe1e0000,  0xffff0f00,  FMT_D9, AM33,	{RM2,
+							 MEM(IMM32_HIGH8_MEM)}},
+{ "mov",	0xfe0a0000,  0xffff0000,  FMT_D9, AM33,	{MEM2(IMM32_HIGH8,RM0),
+							 RN2}},
+{ "mov",	0xfe1a0000,  0xffff0000,  FMT_D9, AM33,	{RM2, MEM2(IMM32_HIGH8,
+								   RN0)}},
+{ "mov",	0xfe8a0000,  0xffff0f00,  FMT_D9, AM33,	{MEM2(IMM32_HIGH8, SP),
+							 RN2}},
+{ "mov",	0xfe9a0000,  0xffff0f00,  FMT_D9, AM33,	{RM2, MEM2(IMM32_HIGH8, 
+								   SP)}},
 /* end-sanitize-am33 */
 
 /* start-sanitize-am33 */
@@ -722,15 +722,17 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "add",	0xf170,	     0xfff0,	 FMT_D0, 0,	{AM1, AN0}},
 { "add",	0x2800,	     0xfc00,	 FMT_S1, 0,	{SIMM8, DN0}},
 { "add",	0xfac00000,  0xfffc0000, FMT_D2, 0,	{SIMM16, DN0}},
-{ "add",	0xfcc00000,  0xfffc0000, FMT_D4, 0,	{IMM32, DN0}},
 { "add",	0x2000,	     0xfc00,	 FMT_S1, 0,	{SIMM8, AN0}},
 { "add",	0xfad00000,  0xfffc0000, FMT_D2, 0,	{SIMM16, AN0}},
-{ "add",	0xfcd00000,  0xfffc0000, FMT_D4, 0,	{IMM32, AN0}},
 { "add",	0xf8fe00,    0xffff00,   FMT_D1, 0,	{SIMM8, SP}},
 { "add",	0xfafe0000,  0xffff0000, FMT_D2, 0,	{SIMM16, SP}},
-{ "add",	0xfcfe0000,  0xffff0000, FMT_D4, 0,	{IMM32, SP}},
 /* start-sanitize-am33 */
 { "add",	0xf97800,    0xffff00,   FMT_D6, AM33,	{RM2, RN0}},
+/* end-sanitize-am33 */
+{ "add",	0xfcc00000,  0xfffc0000, FMT_D4, 0,	{IMM32, DN0}},
+{ "add",	0xfcd00000,  0xfffc0000, FMT_D4, 0,	{IMM32, AN0}},
+{ "add",	0xfcfe0000,  0xffff0000, FMT_D4, 0,	{IMM32, SP}},
+/* start-sanitize-am33 */
 { "add",	0xfb780000,  0xffff0000, FMT_D7, AM33,	{SIMM8, RN02}},
 { "add",	0xfd780000,  0xffff0000, FMT_D8, AM33,	{SIMM24, RN02}},
 { "add",	0xfe780000,  0xffff0000, FMT_D9, AM33,	{IMM32_HIGH8, RN02}},
@@ -754,10 +756,12 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "sub",	0xf120,	     0xfff0,	 FMT_D0, 0,	{DM1, AN0}},
 { "sub",	0xf110,	     0xfff0,	 FMT_D0, 0,	{AM1, DN0}},
 { "sub",	0xf130,	     0xfff0,	 FMT_D0, 0,	{AM1, AN0}},
+/* start-sanitize-am33 */
+{ "sub",	0xf99800,    0xffff00,   FMT_D6, AM33,	{RM2, RN0}},
+/* end-sanitize-am33 */
 { "sub",	0xfcc40000,  0xfffc0000, FMT_D4, 0,	{IMM32, DN0}},
 { "sub",	0xfcd40000,  0xfffc0000, FMT_D4, 0,	{IMM32, AN0}},
 /* start-sanitize-am33 */
-{ "sub",	0xf99800,    0xffff00,   FMT_D6, AM33,	{RM2, RN0}},
 { "sub",	0xfb980000,  0xffff0000, FMT_D7, AM33,	{SIMM8, RN02}},
 { "sub",	0xfd980000,  0xffff0000, FMT_D8, AM33,	{SIMM24, RN02}},
 { "sub",	0xfe980000,  0xffff0000, FMT_D9, AM33,	{IMM32_HIGH8, RN02}},
@@ -824,11 +828,13 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "cmp",	0xb000,	     0xf000,	 FMT_S1, 0,	{IMM8, AN01}},
 { "cmp",	0xb0,	     0xf0,	 FMT_S0, 0,	{AM1, AN0}},
 { "cmp",	0xfac80000,  0xfffc0000, FMT_D2, 0,	{SIMM16, DN0}},
-{ "cmp",	0xfcc80000,  0xfffc0000, FMT_D4, 0,	{IMM32, DN0}},
 { "cmp",	0xfad80000,  0xfffc0000, FMT_D2, 0,	{IMM16, AN0}},
-{ "cmp",	0xfcd80000,  0xfffc0000, FMT_D4, 0,	{IMM32, AN0}},
 /* start-sanitize-am33 */
 { "cmp",	0xf9d800,    0xffff00,   FMT_D6, AM33,	{RM2, RN0}},
+/* end-sanitize-am33 */
+{ "cmp",	0xfcc80000,  0xfffc0000, FMT_D4, 0,	{IMM32, DN0}},
+{ "cmp",	0xfcd80000,  0xfffc0000, FMT_D4, 0,	{IMM32, AN0}},
+/* start-sanitize-am33 */
 { "cmp",	0xfbd80000,  0xffff0000, FMT_D7, AM33,	{SIMM8, RN02}},
 { "cmp",	0xfdd80000,  0xffff0000, FMT_D8, AM33,	{SIMM24, RN02}},
 { "cmp",	0xfed80000,  0xffff0000, FMT_D9, AM33,	{IMM32_HIGH8, RN02}},
@@ -840,11 +846,13 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "and",	0xf200,	     0xfff0,	 FMT_D0, 0,	{DM1, DN0}},
 { "and",	0xf8e000,    0xfffc00,   FMT_D1, 0,	{IMM8, DN0}},
 { "and",	0xfae00000,  0xfffc0000, FMT_D2, 0,	{IMM16, DN0}},
-{ "and",	0xfce00000,  0xfffc0000, FMT_D4, 0,	{IMM32, DN0}},
 { "and",	0xfafc0000,  0xffff0000, FMT_D2, 0,	{IMM16, PSW}},
 /* start-sanitize-am33 */
 { "and",	0xfcfc0000,  0xffff0000, FMT_D4, AM33,	{IMM32, EPSW}},
 { "and",	0xf90900,    0xffff00,   FMT_D6, AM33,	{RM2, RN0}},
+/* end-sanitize-am33 */
+{ "and",	0xfce00000,  0xfffc0000, FMT_D4, 0,	{IMM32, DN0}},
+/* start-sanitize-am33 */
 { "and",	0xfb090000,  0xffff0000, FMT_D7, AM33,	{IMM8, RN02}},
 { "and",	0xfd090000,  0xffff0000, FMT_D8, AM33,	{IMM24, RN02}},
 { "and",	0xfe090000,  0xffff0000, FMT_D9, AM33,	{IMM32_HIGH8, RN02}},
@@ -856,11 +864,13 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "or",		0xf210,	     0xfff0,	 FMT_D0, 0,	{DM1, DN0}},
 { "or",		0xf8e400,    0xfffc00,   FMT_D1, 0,	{IMM8, DN0}},
 { "or",		0xfae40000,  0xfffc0000, FMT_D2, 0,	{IMM16, DN0}},
-{ "or",		0xfce40000,  0xfffc0000, FMT_D4, 0,	{IMM32, DN0}},
 { "or",		0xfafd0000,  0xffff0000, FMT_D2, 0,	{IMM16, PSW}},
 /* start-sanitize-am33 */
 { "or",		0xfcfd0000,  0xffff0000, FMT_D4, AM33,	{IMM32, EPSW}},
 { "or",		0xf91900,    0xffff00,   FMT_D6, AM33,	{RM2, RN0}},
+/* end-sanitize-am33 */
+{ "or",		0xfce40000,  0xfffc0000, FMT_D4, 0,	{IMM32, DN0}},
+/* start-sanitize-am33 */
 { "or",		0xfb190000,  0xffff0000, FMT_D7, AM33,	{IMM8, RN02}},
 { "or",		0xfd190000,  0xffff0000, FMT_D8, AM33,	{IMM24, RN02}},
 { "or",		0xfe190000,  0xffff0000, FMT_D9, AM33,	{IMM32_HIGH8, RN02}},
@@ -871,13 +881,16 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 /* end-sanitize-am33 */
 { "xor",	0xf220,	     0xfff0,	 FMT_D0, 0,	{DM1, DN0}},
 { "xor",	0xfae80000,  0xfffc0000, FMT_D2, 0,	{IMM16, DN0}},
-{ "xor",	0xfce80000,  0xfffc0000, FMT_D4, 0,	{IMM32, DN0}},
 /* start-sanitize-am33 */
 { "xor",	0xf92900,    0xffff00,   FMT_D6, AM33,	{RM2, RN0}},
+/* end-sanitize-am33 */
+{ "xor",	0xfce80000,  0xfffc0000, FMT_D4, 0,	{IMM32, DN0}},
+/* start-sanitize-am33 */
 { "xor",	0xfb290000,  0xffff0000, FMT_D7, AM33,	{IMM8, RN02}},
 { "xor",	0xfd290000,  0xffff0000, FMT_D8, AM33,	{IMM24, RN02}},
 { "xor",	0xfe290000,  0xffff0000, FMT_D9, AM33,	{IMM32_HIGH8, RN02}},
 /* end-sanitize-am33 */
+
 { "not",	0xf230,	     0xfffc,	 FMT_D0, 0,	{DN0}},
 /* start-sanitize-am33 */
 { "not",	0xf93900,    0xffff00,   FMT_D6, AM33,	{RN02}},