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| author | Jan Beulich <jbeulich@novell.com> | 2018-03-22 08:31:43 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2018-03-22 08:31:43 +0100 |
| commit | d6793fa1acf384a93c83db6eb916e3b9eedd9ef4 (patch) | |
| tree | 8c6ac3bc26803c338b3ae5a9edce2ff5f025f7e6 /opcodes/m10200-opc.c | |
| parent | f776822506b417ce25170c67c33cc05870b37adf (diff) | |
| download | gdb-d6793fa1acf384a93c83db6eb916e3b9eedd9ef4.zip gdb-d6793fa1acf384a93c83db6eb916e3b9eedd9ef4.tar.gz gdb-d6793fa1acf384a93c83db6eb916e3b9eedd9ef4.tar.bz2 | |
x86/Intel: fix fallout from earlier template folding
While many templates allowing multiple suitably matching XMM/YMM/ZMM
operand sizes can be folded, a few need to be split in order to not
wrongly accept "xmmword ptr" operands when only XMM registers are
permitted (and memory operands are more narrow). Add a test case
validating this.
Diffstat (limited to 'opcodes/m10200-opc.c')
0 files changed, 0 insertions, 0 deletions