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| author | Tamar Christina <tamar.christina@arm.com> | 2019-02-07 16:55:23 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2019-02-07 16:56:35 +0000 |
| commit | 6456d318aaa7ea35511dad1f2facf0fb984972e5 (patch) | |
| tree | 9ef3c078613f20160ad3e37d961e8da7dec79150 /opcodes/lm32-opinst.c | |
| parent | b2abe1bd8149dd9ad64432f620c3a034bf23a5fe (diff) | |
| download | gdb-6456d318aaa7ea35511dad1f2facf0fb984972e5.zip gdb-6456d318aaa7ea35511dad1f2facf0fb984972e5.tar.gz gdb-6456d318aaa7ea35511dad1f2facf0fb984972e5.tar.bz2 | |
AArch64: Add verifier for By elem Single and Double sized instructions.
The AArch64 instruction set has cut-outs inside instructions encodings for
when a given encoding that would normally fall within the encoding space of
an instruction is instead undefined.
This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case
where sz:L == 11.
gas/ChangeLog:
PR binutils/23212
* testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test.
* testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test.
opcodes/ChangeLog:
PR binutils/23212
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
* aarch64-opc.c (verify_elem_sd): New.
(fields): Add FLD_sz entr.
* aarch64-tbl.h (_SIMD_INSN): New.
(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
fmulx scalar and vector by element isns.
Diffstat (limited to 'opcodes/lm32-opinst.c')
0 files changed, 0 insertions, 0 deletions