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| author | Richard Sandiford <richard.sandiford@arm.com> | 2022-01-06 16:22:54 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2022-01-06 16:22:54 +0000 |
| commit | 27297937e0c648cdf115ecbceb4ba25dfefe7492 (patch) | |
| tree | 4cf2cea710ecf9e12d951a994f90edbdb03223ec /opcodes/lm32-opc.h | |
| parent | 41e321a8973edf99f69eb3f11cc076a69be726af (diff) | |
| download | gdb-27297937e0c648cdf115ecbceb4ba25dfefe7492.zip gdb-27297937e0c648cdf115ecbceb4ba25dfefe7492.tar.gz gdb-27297937e0c648cdf115ecbceb4ba25dfefe7492.tar.bz2 | |
aarch64: Add support for new SME instructions
This patch adds support for three new SME instructions: ADDSPL,
ADDSVL and RDSVL. They behave like ADDPL, ADDVL and RDVL, but read
the streaming vector length instead of the current vector length.
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Add ADDSPL, ADDSVL and RDSVL.
* aarch64-dis-2.c: Regenerate.
gas/
* testsuite/gas/aarch64/sme.s, testsuite/gas/aarch64/sme.d: Add tests
for ADDSPL, ADDSVL and RDSVL.
Diffstat (limited to 'opcodes/lm32-opc.h')
0 files changed, 0 insertions, 0 deletions