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authorNick Clifton <nickc@redhat.com>2004-10-27 09:30:09 +0000
committerNick Clifton <nickc@redhat.com>2004-10-27 09:30:09 +0000
commit4030fa5ade3caa531bb7dbe9717886681b187a71 (patch)
treee88489f1fd9187714c6a42d1a58e43ab85ca2d37 /opcodes/iq2000-asm.c
parent6f372e19e749d6cb170f995b673e7651a4e3715e (diff)
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Add an index operand to some of the iq2000 co-processor instructions
Diffstat (limited to 'opcodes/iq2000-asm.c')
-rw-r--r--opcodes/iq2000-asm.c26
1 files changed, 15 insertions, 11 deletions
diff --git a/opcodes/iq2000-asm.c b/opcodes/iq2000-asm.c
index 62d03f8..3db5d90 100644
--- a/opcodes/iq2000-asm.c
+++ b/opcodes/iq2000-asm.c
@@ -48,16 +48,22 @@ static const char * parse_insn_normal
/* -- assembler routines inserted here. */
/* -- asm.c */
+
+#include "safe-ctype.h"
+
+static int iq2000_cgen_isa_register PARAMS ((const char **));
+static const char * parse_jtargq10 PARAMS ((CGEN_CPU_DESC, const char **, int, int, enum cgen_parse_operand_result *, unsigned long *));
static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+static const char * parse_mlo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
/* Special check to ensure that instruction exists for given machine */
int
iq2000_cgen_insn_supported (cd, insn)
CGEN_CPU_DESC cd;
- CGEN_INSN *insn;
+ const CGEN_INSN *insn;
{
int machs = cd->machs;
@@ -88,7 +94,7 @@ static int iq2000_cgen_isa_register (strp)
return 1;
}
}
- if (**strp == '%' && tolower((*strp)[1]) != 'l' && tolower((*strp)[1]) != 'h')
+ if (**strp == '%' && TOLOWER((*strp)[1]) != 'l' && TOLOWER((*strp)[1]) != 'h')
return 1;
return 0;
}
@@ -103,7 +109,6 @@ parse_mimm (cd, strp, opindex, valuep)
long *valuep;
{
const char *errmsg;
- long value;
/* Verify this isn't a register */
if (iq2000_cgen_isa_register (strp))
@@ -116,7 +121,7 @@ parse_mimm (cd, strp, opindex, valuep)
if (errmsg == NULL)
{
long x = (-value) & 0xFFFF0000;
- if (x != 0 && x != 0xFFFF0000)
+ if (x != 0 && x != (long) 0xFFFF0000)
errmsg = _("immediate value out of range");
else
*valuep = (-value & 0xFFFF);
@@ -135,7 +140,6 @@ parse_imm (cd, strp, opindex, valuep)
unsigned long *valuep;
{
const char *errmsg;
- long value;
if (iq2000_cgen_isa_register (strp))
errmsg = _("immediate value cannot be register");
@@ -147,7 +151,7 @@ parse_imm (cd, strp, opindex, valuep)
if (errmsg == NULL)
{
long x = value & 0xFFFF0000;
- if (x != 0 && x != 0xFFFF0000)
+ if (x != 0 && x != (long) 0xFFFF0000)
errmsg = _("immediate value out of range");
else
*valuep = (value & 0xFFFF);
@@ -163,8 +167,8 @@ parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
- int reloc;
- enum cgen_parse_operand_result *type_addr;
+ int reloc ATTRIBUTE_UNUSED;
+ enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED;
unsigned long *valuep;
{
const char *errmsg;
@@ -345,6 +349,9 @@ iq2000_cgen_parse_operand (cd, opindex, strp, fields)
switch (opindex)
{
+ case IQ2000_OPERAND__INDEX :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND__INDEX, &fields->f_index);
+ break;
case IQ2000_OPERAND_BASE :
errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rs);
break;
@@ -385,9 +392,6 @@ iq2000_cgen_parse_operand (cd, opindex, strp, fields)
case IQ2000_OPERAND_EXECODE :
errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_EXECODE, &fields->f_excode);
break;
- case IQ2000_OPERAND_F_INDEX :
- errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_F_INDEX, &fields->f_index);
- break;
case IQ2000_OPERAND_HI16 :
errmsg = parse_hi16 (cd, strp, IQ2000_OPERAND_HI16, &fields->f_imm);
break;