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| author | H.J. Lu <hjl.tools@gmail.com> | 2007-11-14 22:31:54 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2007-11-14 22:31:54 +0000 |
| commit | 4f8631b1d4f2b34021d2e4827a3d392684f3243d (patch) | |
| tree | 8cdf13f448702ed652ca12cc7677a581c1f45228 /opcodes/ia64-waw.tbl | |
| parent | 07f397aba39f619db4fdce42c9e91cb07dd4dc68 (diff) | |
| download | gdb-4f8631b1d4f2b34021d2e4827a3d392684f3243d.zip gdb-4f8631b1d4f2b34021d2e4827a3d392684f3243d.tar.gz gdb-4f8631b1d4f2b34021d2e4827a3d392684f3243d.tar.bz2 | |
gas/
2007-11-14 Tristan Gingold <gingold@adacore.com>
* config/tc-ia64.c (AR_RUC): Defined.
(ar): Add "ar.ruc".
(specify_resource): Handle AR_RUC like AR_ITC.
gas/testsuite/
2007-11-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/ia64/dv-raw-err.s: Add tests for ar.ruc.
* gas/ia64/dv-waw-err.s: Likewise.
* gas/ia64/invalid-ar.s: Likewise.
* gas/ia64/regs.s: Add tests for ar.ruc and ar44.
* gas/ia64/dv-raw-err.l: Updated.
* gas/ia64/dv-waw-err.l: Likewise.
* gas/ia64/invalid-ar.l: Likewise.
* gas/ia64/regs.d: Likewise.
opcodes/
2007-11-14 H.J. Lu <hongjiu.lu@intel.com>
* ia64-ic.tbl: Updated for Itanium 9100 series.
* ia64-raw.tbl: Likewise.
* ia64-waw.tbl: Likewise.
* ia64-asmtab.c: Regenerated.
2007-11-14 Tristan Gingold <gingold@adacore.com>
* ia64-dis.c (print_insn_ia64): Handle ar.ruc.
* ia64-gen.c (lookup_regindex): Likewise.
Diffstat (limited to 'opcodes/ia64-waw.tbl')
| -rw-r--r-- | opcodes/ia64-waw.tbl | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/opcodes/ia64-waw.tbl b/opcodes/ia64-waw.tbl index a555dab..4524cb6 100644 --- a/opcodes/ia64-waw.tbl +++ b/opcodes/ia64-waw.tbl @@ -32,9 +32,10 @@ AR[PFS]; br.call, brl.call; br.call, brl.call; none AR[PFS]; br.call, brl.call; IC:mov-to-AR-PFS; impliedF AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF AR[RSC]; IC:mov-to-AR-RSC; IC:mov-to-AR-RSC; impliedF +AR[RUC]; IC:mov-to-AR-RUC; IC:mov-to-AR-RUC; impliedF AR[SSD]; IC:mov-to-AR-SSD; IC:mov-to-AR-SSD; impliedF AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; IC:mov-to-AR-UNAT, st8.spill; impliedF -AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; IC:none; none +AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 46-47, 67-111; IC:none; IC:none; none AR%, % in 48 - 63, 112-127; IC:mov-to-AR-ig+1; IC:mov-to-AR-ig+1; impliedF BR%, % in 0 - 7; br.call+1, brl.call+1; IC:mov-to-BR+1; impliedF BR%, % in 0 - 7; IC:mov-to-BR+1; IC:mov-to-BR+1; impliedF |