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authorRichard Henderson <rth@redhat.com>2002-12-03 18:15:48 +0000
committerRichard Henderson <rth@redhat.com>2002-12-03 18:15:48 +0000
commita823923bf657b448ef2ef71ab7b8fad2f31cd818 (patch)
tree8b05668c014a8c78fd375edc8d9af3daa23efd7f /opcodes/ia64-opc-m.c
parent144da3c187ed993a76044e4e12a655dd760ef129 (diff)
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include/opcode/
* ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV. bfd/ * cpu-ia64-opc.c (elf64_ia64_operands): Add ldxmov entry. opcodes/ * ia64-opc-m.c: Add ld8.mov. * ia64-asmtab.c: Regenerate. gas/ * config/tc-ia64.c (operand_match): Add IA64_OPND_LDXMOV case. gas/testsuite/ * gas/ia64/ldxmov-1.[ds]: New. * gas/ia64/ldxmov-2.[ls]: New. * gas/ia64/ia64.exp: Run them.
Diffstat (limited to 'opcodes/ia64-opc-m.c')
-rw-r--r--opcodes/ia64-opc-m.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/ia64-opc-m.c b/opcodes/ia64-opc-m.c
index ba59d1d..654f112 100644
--- a/opcodes/ia64-opc-m.c
+++ b/opcodes/ia64-opc-m.c
@@ -265,6 +265,10 @@ struct ia64_opcode ia64_opcodes_m[] =
{"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}, EMPTY},
{"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}, EMPTY},
+ /* Pseudo-op that generates ldxmov relocation. */
+ {"ld8.mov", M, OpMXX6aHint (4, 0, 0, 0x03, 0),
+ {R1, MR3, IA64_OPND_LDXMOV}, EMPTY},
+
/* Integer load w/increment by register. */
#define LDINCREG(c,h) M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC, 0, NULL
{"ld1", LDINCREG (0x00, 0)},