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| author | Jan Beulich <jbeulich@novell.com> | 2005-01-31 08:48:32 +0000 |
|---|---|---|
| committer | Jan Beulich <jbeulich@novell.com> | 2005-01-31 08:48:32 +0000 |
| commit | 60b9a617725df23ea629c34a83919bf320082a7d (patch) | |
| tree | 41c516899c81c93b7ef9997355ee9e56e126c483 /opcodes/ia64-opc-i.c | |
| parent | e901b190a91d42356660e45e459c60fac24b2e7d (diff) | |
| download | gdb-60b9a617725df23ea629c34a83919bf320082a7d.zip gdb-60b9a617725df23ea629c34a83919bf320082a7d.tar.gz gdb-60b9a617725df23ea629c34a83919bf320082a7d.tar.bz2 | |
gas/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (parse_operands): Also handle alloc without first
input being ar.pfs.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/pseudo.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
opcodes/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* ia64-gen.c (NELEMS): Define.
(shrink): Generate alias with missing second predicate register when
opcode has two outputs and these are both predicates.
* ia64-opc-i.c (FULL17): Define.
(ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
here to generate output template.
(TBITCM, TNATCM): Undefine after use.
* ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
first input. Add ld16 aliases without ar.csd as second output. Add
st16 aliases without ar.csd as second input. Add cmpxchg aliases
without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
ar.ccv as third/fourth inputs. Consolidate through...
(CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
* ia64-asmtab.c: Regenerate.
Diffstat (limited to 'opcodes/ia64-opc-i.c')
| -rw-r--r-- | opcodes/ia64-opc-i.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/opcodes/ia64-opc-i.c b/opcodes/ia64-opc-i.c index 86440f7..dcc2d77 100644 --- a/opcodes/ia64-opc-i.c +++ b/opcodes/ia64-opc-i.c @@ -95,6 +95,8 @@ (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \ (mOp | mX3 | mXb | mIh | mWh | mTag13) +#define FULL17 ((ia64_insn)0x10ff001fc0LL) + /* Used to initialise unused fields in ia64_opcode struct, in order to stop gcc from complaining. */ #define EMPTY 0,0,NULL @@ -126,6 +128,8 @@ struct ia64_opcode ia64_opcodes_i[] = #undef MOV {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY}, {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY}, + /* Don't remove one of the seemingly redundant FULL17-s. */ + {"mov", I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL}, {"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY}, {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY}, {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY}, @@ -181,6 +185,7 @@ struct ia64_opcode ia64_opcodes_i[] = {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)}, {"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)}, #undef TBIT +#undef TBITCM #define TNAT(a,b,c,d) \ I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY #define TNATCM(a,b,c,d) \ @@ -202,6 +207,7 @@ struct ia64_opcode ia64_opcodes_i[] = {"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)}, {"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)}, #undef TNAT +#undef TNATCM {"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY}, {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY}, |